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适于低电源电压应用的新型MOS自举采样开关 被引量:2

A Novel MOS Bootstrapped Sampling Switch for Low Supply Voltage
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摘要 提出了一种适合低电源电压应用的新型MOS自举采样开关电路。通过"复制"自举电容和采样开关作为电荷损耗检测电路,并将检测出的电压降低值重新加到自举电容上,解决了传统MOS自举采样开关在低电源电压下工作时的电荷分享问题。基于0.18μm标准CMOS工艺,对电路进行了仿真。结果显示,在输入频率为60MHz、峰-峰值为1V、采样频率为125MHz时,与传统自举采样电路相比,新型自举采样电路采样开关管具有更低的导通电阻,无杂散动态范围(SFDR)提高了8dB,特别适合在低压高速A/D转换器中使用。 A novel MOS bootstrapped sampling switch suitable for low supply voltage application was proposed.In this circuit,a duplicate sampling circuit,which estimated the charge loss and added it in series to bootstrap capacitor,was used to solve charge sharing problem subjected to conventional bootstrapped sampling switch operating at low voltage supply.The circuit was simulated based on 0.18 μm standard CMOS process.Simulation results showed that,compared with the conventional bootstrapped switch,the proposed circuit reduced on-resistance of the sampling switch and improved spurious free dynamic range(SFDR) by 8 dB for 60 MHz and 1 V(VP-P) input signal at 125 MS/s sampling rate.This method is especially useful for low-voltage and high-speed A/D converters.
出处 《微电子学》 CAS CSCD 北大核心 2011年第6期794-798,共5页 Microelectronics
关键词 采样开关 自举电路 电荷分享 无杂散动态范围 Sampling switch Bootstrapped circuit Charge sharing SFDR
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参考文献8

  • 1帅欣,董会宁,黄竹.一种低电压低功耗Rail-to-Rail CMOS运算放大器的设计[J].重庆邮电大学学报(自然科学版),2007,19(6):658-661. 被引量:1
  • 2RAZAVI B. Principles of data conversion system design[M]. New Jersey: IEEE Press, 1995.
  • 3ABO A M, GRAY P R. A 1.5 V 10-bit 14. 3 MS/s CMOS pipeline analogto-digital converter[J].IEEE J Sol Sta Circ, 1999, 34(5): 599-606.
  • 4DESSOUKY M, KAISER A. Input switch configura tion suitable for rail-to-rail operation of switched op amp circuits [J]. Elec Lett, 1999, 35(1): 8-10.
  • 5LILLEBREKKE C, WULFF C, YTTERDAL T. Boot strapped switch in low-voltage digital 90 nm CMOS tech nology [C] //23rd Norchip Conf. Oulu, Finland. 2005 234-236.
  • 6WALTARI M. Circuit techniques for low-voltage and high-speed A/D converters [D]. Espeo, Finland: Helsinki University of Technology, 2002.
  • 7戴澜,姜岩峰,刘文楷.12位50 MHz流水线ADC采样保持电路实现[J].微电子学,2010,40(4):503-505. 被引量:6
  • 8SARRAJ M. Sample and hold design techniques for Nyquist ADC design [C] // IEEE Dallas Circ Syst Works (DCAS). Dallas, TA, USA. 2009: 1-4.

二级参考文献14

  • 1段晓峰,陈向东,黎文模.低压低功耗CMOS电流反馈运算放大器的设计[J].重庆邮电学院学报(自然科学版),2006,18(2):171-174. 被引量:4
  • 2[2]HOGERVORST R,HUIJSING J H.Design of Low-Voltage Low-Power Operational Amplifier Cells[M].Boston:Kluwer Academic Publishers,1996:67-75.
  • 3[3]GIUSEPPE F,WILLY S.A Rail-to-Rail Constant-gm Low-Voltage CMOS Operational Transconductance Amplifier[J].IEEE Journal of Solid-State Circuits,1997,32(10):1 563-1 567.
  • 4[4]HOGERVORST R,TERO J P,HUIJSING J H.Compact CMOS Constant-gm Rail-to-Rail Input Stage with gm Control by an Electronic Zener Diode[C]// Proceeding ESSCIRC 1995,19-21,Sep.Lille,France:[s.n.],1995:78-81.
  • 5[5]HUIJSING J H.Operational Amplifiers-Theory and Design[M].北京:清华大学出版社,2006:106-112.
  • 6[6]LANGEN K,HUIJSING J H.Compact Low Voltage Power Efficient Operational Amplifier Cells for VLSI[J].IEEE Journal of Solid-State Circuits,1998,33(10):1 483-1 496.
  • 7[7]HUIJSING J H,LINEBARGER D.Low-Voltage Operational Amplifiers with Rail-to-Rail Input and Output Stage[J].IEEE Journal of Solid-State Circuits,1985,SC-20(6):1 144-1 150.
  • 8[8]ALLEN P E,DOUGLAS R H.CMOS Analogy Circuit Design[M].2nd.ed,冯军,李智群,译.北京:电子工业出社,2006:206-218.
  • 9LEWIS S H,GRAY P R.A pipelined 5-M sample/s 9-bit analog-to-digital converter[J].IEEE J Sol Sta Circ,1987,22(6):954-959.
  • 10YANG Wenhua,KELLY D,MEHR I,et al.A 3-V 340 mW 14-b 75-Ms/s CMOS ADC with 85-dB SFDR at Nyquist input[J].IEEE J Sol Sta Circ,2001,36(12):1931-1936.

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