摘要
给出了使用verilog HDL语言对锁相环进行基于FPGA的全数字系统设计,以及对其性能进行分析和计算机仿真的具体方法。该方法采用综合仿真工具QuartusⅡ8.0来对数字锁相环进行输入设计、功能时序仿真及器件编程。仿真结果表明:该方法可通过在传统数字锁相环基本结构的基础上增加自动变模控制模块来有效解决缩短捕捉时间和减小同步误差之间的矛盾。
A DPLL based on FPGA by using verilog HDL language is introduced for analyzing the system perfor mance and computer simulation. A comprehensive simulation tool Quartus Ⅱ 8.0. was used to perform input, function al and timing simulation and device programming for digital phase-locked loop. Simulation results show that the automat ic variable module should be added to the traditional digital PLL to shorten the capture time and reduce the conflict a mong the synchronization error.
出处
《物联网技术》
2011年第10期76-78,81,共4页
Internet of things technologies
基金
中央高校基本科研业务费资助(103.1.2E022050205)
