摘要
针对图像处理的实时性要求越来越高,本文研究了以FPGA为主要硬件平台,使用Verilog硬件描述语言来对采集的视频信号进行中值滤波预处理。在传统中值滤波算法的基础上,充分利用了系统的硬件资源,提出了一种基于FPGA的新型流水线中值滤波设计方法。与传统方法相比较,该方法极大地提高了系统的处理速度以及保证了实时性的要求,可以应用于实时性要求较高的场合。最后还对整个系统的实现方法在QuartusII软件中进行了仿真,通过仿真结果验证了其可行性。
As real time requirement on image settlement goes more and more precise, this paper aims to take PFGA as hardware desktop and make use of Verilog hardware description language to have a median filter on video signal. On the basis of the traditional median filtering algorithm, this paper makes the best of system hardware resource, so here comes a design method based on assembly line. Compared with traditional designs, such design has greatly accelerated processing speed and ensured real time requirement, hence it can be used in some place where needs more real time requirement. At last, such design has had an simulation to the whole system＇s implementation method with the environment of QuartusII , and according to such simulation its feasibility has been testified.
出处
《电子测试》
2011年第12期50-53,共4页
Electronic Test
