摘要
It is an important problem that we implement floating point trigonometric functions of high precision with suitable hardware cost for high performance in digit image processing. The coordinate rotational digital computer （CORDIC） arithmetic to is used to solve the above problem in this paper. In order to increase the speed of operation, it chooses the pipeline architecture. The results are disposed by IEEE-754 standard. The CORDIC architecture is modeled by using the verilog HDL and verified with MATLAB program and ModelSim 6.2SE tool. A 32 bits radix-2 CORDIC architecture was implemented on the available FPGA platform. The entire CORDIC architecture operated at 126.34 MHz of clock rate with a power consumption of 318.56 mW. Its theoretical background, procedures, simulation results and conclusions are presented in this paper.
It is an important problem that we implement floating point trigonometric functions of high precision with suitable hardware cost for high performance in digit image processing. The coordinate rotational digital computer （CORDIC） arithmetic to is used to solve the above problem in this paper. In order to increase the speed of operation, it chooses the pipeline architecture. The results are disposed by IEEE-754 standard. The CORDIC architecture is modeled by using the verilog HDL and verified with MATLAB program and ModelSim 6.2SE tool. A 32 bits radix-2 CORDIC architecture was implemented on the available FPGA platform. The entire CORDIC architecture operated at 126.34 MHz of clock rate with a power consumption of 318.56 mW. Its theoretical background, procedures, simulation results and conclusions are presented in this paper.
基金
supported by the Shanghai AM Foundation(Grant No.09700714000)
