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一种支持H.264 High Profile的高效可重构反变换VLSI结构 被引量：1

An Efficient Reconfigurable VLSI Architecture for H.264 High Profile Inverse Transform
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摘要 本文针对H.264 Fidelity Range Extensions(FRExt,High Profile)解码过程中扩展的所有变换,采用二维矩阵分解和基于矩阵运算提取公共因子的操作,利用通用运算单元来设计高效的可重构VLSI结构.该结构不但节省面积(可重构变换结构只消耗了4807门电路),并且具有高性能(采用TSMC 0.13微米工艺,在150MHz的时钟频率下工作,该电路可以达到1.2G pixels/s的吞吐率,支持分辨率为4096×2048、每秒60帧的视频实时解码需求).根据DTUA(吞吐率和电路规模的比值)作为效率因子,本设计在支持H.264 High Profile所有变换的设计中具有最高的效率. H.264 High Profile proposes the new 8×8 integer transform which achieves average bit-rate reduction of around 10% for HD material.This paper presents an efficient architecture for H.264 multiple block-size inverse transform.2-D transform decomposition and common matrix operation extraction were applied to design general processing elements to simplify the implementation of transforms.The proposed architecture is both area-efficient（4807gates） and high performance（can provide real-time decoding of 4096×2048@60fps High Profile in 150MHz,1.2G pixels/s data throughput rate,using TSMC 0.13 μm）.This paper supporting all of the H.264 high profile transforms is the most efficient one,compared with the existing designs with the Data Throughput rate per Unit Area（DTUA） adopted as the comparison index.
作者 陆晓凤 刘锋 佟冬 王克义
机构地区 北京大学微处理器研究开发中心 北京大学深圳研究生院
出处 《电子学报》 EI CAS CSCD 北大核心 2011年第5期1072-1076,共5页 Acta Electronica Sinica
关键词 整数变换 HIGH PROFILE H.264 integer transform high profile H.264
分类号 TP302 [自动化与计算机技术—计算机系统结构]
  • 相关文献

参考文献12

  • 1Liu Ling-zhi, Qiu Lin, Rong Meng-tian, Jiang Li. A 2-D for- ward/inverse integer transform processor of H. 264 based on highly-parallel architecture [ A]. 4th IEEE International Work- shop on System-on-Chip for Real-time Applications[ C]. Banff, Alberta, Canada: IEEE Computer Society, 2(D4.158 - 161.
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  • 4Woong Hwangbo, Jaemoon Kim, Chong-Min Kyung.A high performance 2-D inverse transform architecture for the H.264/AVC decoder[ A].IEEE International Symposium on Circuits and Systems[C].LA,USA:IEEE,2007.1613 1616.
  • 5曹伟,洪琪,侯慧,童家榕,来金梅,闵昊,荆明娥.一种用于H.264编解码的新型高效可重构多变换VLSI结构[J].电子学报,2009,37(4):673-677. 被引量：7
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  • 7Tu-Chih Wang, Yu-Wen Huang,Hung-Chi Fang,and Hang-Gee Chen. Parallel 4 × 4 2D transform and inverse transform architec- ture for MPEG-4 AVC/H.264[A]. IEEE International Sympo- sium on Circuits and Systems [ C ]. Bangkok, Thailand: IEEE, 2003:800- 803.
  • 8Yu Li, Yun He, Shun-liang Mei.A highly parallel joint VLSI architecture for transforms in H. 264/AVC[J].Journal of Signal Processing Systems,2008,50(1) : 19 - 32.
  • 9Yu-Wen Huang, Bing-Yu Hsieh, Tung-Chien Chen, Liang-Gee Chen.Analysis, fast algorithm, and VLSI architecture design for H. 264/AVC intra-frame coder[J].IEEE Transaction on Circuits Systems for Video Technology,2005,15(3):378 401.
  • 10Ihab Amer, Wael Badawy, Graham Jullien. A high-performance hardware implementation of the H. 264 simplified 8 × 8 trans- formation and quantization[ A]. International Conference on A- cottstics, Speech, and Signal Processing [ C ]. Philadelphia, PA, USA: IEEE Signal Processing Society,2005.1137- 1140.

二级参考文献7

  • 1A Joch, F Kossentini, H Schwarz, T Wiegand, and G J Sullivan. Performance comparison of video coding standards using lagragian coder control[ A]. Proc IEEE, Int Conf Image Processing[ C] .New York, USA. 2002.501 - 504.
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  • 3Yu-Wen Huang,Bing-Yu Hsieh, Tung-Chien Chen, and Liang- Gee Chert. Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra flame coder[ J]. IF.EE Transactions on Circuits and Systems for Video Technology,March 2005,15 (3) :378 - 401.
  • 4Kuan-Hung Chen, Jiun-In Guo and Jinn-Shyan Wang. A highperformance direct 2-D transform coding IP design for MPEG-4 AVC/H.264[ J]. IEEE Transactions on Circuits and Systems for Video Technology,April 2006,16(4) :472 - 483.
  • 5L Z Liu,Q Lin,M T Rong, J Li.A 2-D forward/inverse integer transform processor of H.264 based on highly-parallel architecture[ A]. Proc IEEE. Int Workshop System-on-Chip Real- Time Applicat [ C]. Banff, Alberta, Canada. Jul 2004. 158 - 161.
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二级引证文献13

电子学报
2011年 第5期

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