摘要
电荷耦合器件(CCD)作为一种新型的光电器件,被广泛地应用于非接触测量。而CCD驱动设计是CCD应用的关键问题之一。为了克服早期CCD驱动电路体积大,设计周期长,调试困难等缺点,以线阵CCD图像传感器TCD1251UD为例,介绍一种利用可编程逻辑器件FPGA实现积分时间和频率同时可调的线阵CCD驱动方法,使用Verilog语言对驱动电路方案进行了硬件描述,采用QuartusⅡ对所设计的时序进行系统仿真。仿真结果表明,该驱动时序的设计方法是可行的。
The charge coupled device （CCD） as a new photoelectric device is widely used in non-contacted measurement. The design of CCD driver is one of the most important aspects of CCD applications. Taking linear CCD image sensor TCD1251UD as example, a driving method of linear array CCD is introduced to make the integration time and frequency tuned simultaneously with a field programmable logical devices FPGA to overcome the disadvantages of big eubage, complicated design and difficult debug in previous CCD driving circuit. Verilog is used to describe the hardware of the driving circuit scheme. QuartusⅡ is adopted to simulate the designed time sequence. The simulation demonstrates that the method is feasible.
出处
《现代电子技术》
2011年第10期206-207,210,共3页
Modern Electronics Technique
关键词
线阵CCD
可编程逻辑器件
积分时间
频率
linear array CCD
programmable logical device
integration time
frequency
