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体硅上外延超薄Si1-xGex用于制备SGOI材料 被引量：2

Growth of ultrathin Si1-xGex Films on Si Substrate for Fabricating SGOI
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摘要 采用减压化学气相沉积的方法在Si衬底上制备了高质量的Si0.75Ge0.25/Si/Si0.86Ge0.14叠层材料,通过TEM、光学显微镜和XRD分析表明,外延的SiGe薄膜具有完好的晶格结构,平整的表面质量,SiGe薄膜处于完全应变状态。通过与Si上外延渐变缓冲层制备的SiGe材料比较发现,使用这种超薄的全应变SiGe叠层材料来制备SGOI,可以大大缩短制备周期,降低制备成本。 High quality Si0.75Ge0.25/Si/Si0.86Ge0.14 films were fabricated on bulk Si substrate by reduced pressure chemical vapor deposition（RPCVD） system.Transmission electron microscopy（TEM） and optical microscopy revealed the epitaxial films were of the perfect crystal quality and good surface morphology.X-ray diffraction measurements indicated that Si0.75Ge0.25 and Si0.86Ge0.14 layers were fully strained.Fabricating SGOI materials with this high quality Si0.75Ge0.25/Si/ Si0.86Ge0.14 films will reduce costs and save time significantly compared with fabricating SGOI materials with conventional graded buffer SiGe films.
作者 薛忠营 张波 魏星 张苗
机构地区 中科院上海微系统与信息技术研究所信息功能材料国家重点实验室 中国科学院研究生院
出处 《功能材料与器件学报》 CAS CSCD 北大核心 2011年第2期147-150,共4页 Journal of Functional Materials and Devices
基金 国家重点基础研究发展计划(2010CB832906) 上海应用材料研究与发展基金(082SYA1001) 新泰课题基金(092XTA1001)
关键词 外延 应变 锗硅 SGOI epitaxy strain SiGe SGOI
分类号 TN304.05 [电子电信—物理电子学]
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参考文献13

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同被引文献30

  • 1陈荔群,周志文,李成,赖虹凯,陈松岩.Si基Ge波导光电探测器的制备和特性研究[J].光电子．激光,2009,20(8):1012-1015. 被引量：10
  • 2李竞春,谭静,杨谟华,张静,徐婉静.Strained-Si pMOSFETs on Very Thin Virtual SiGe Substrates[J].Journal of Semiconductors,2005,26(5):881-885. 被引量：2
  • 3Moutanabbir O, Hahnel A, Reiche M, et al. Strain Nano-Engineering: SSOI as a Playground [ J ]. ECS Transactions, 2011,35 (5) :43 - 50.
  • 4Thompson S E, Guangyu S, C Youn Sung, et al. Uni- axial-process-induced strained-Si: extending the CMOSroadmap [ J]. Electron Devices, IEEE Transactions on, 2006,53 (5) : 1010 - 1020.
  • 5Chidambaram P R, Smith B A, Hall L H, et al. 35 drive current improvement from recessed - SiGe drain extensions on 37 nm gate length PMOS[C]. In:VLSI Technology, 2004. Digest of Technical Papers. 2004 Symposium on. 2004.
  • 6Kah - Wee A, W Hoong - Shing, Balasubramanian N, et al. Enhanced performance in strained n-FET with double-recessed Si: C source/drain and lattice-mis- matched SiGe strain-transfer structure (STS) [ C ]. In: Semiconductor Device Research Symposium, 2007 In- ternational. 2007.
  • 7Morin P, Ortolland C, Mastromatteo E, et al. Mecha- nisms of stress generation within a polysilicon gate for nMOSFET performance enhancement [ J ]. Materials Science and Engineering B-Solid State Materials for Ad- vanced Technology, 2006,135 ( 3 ) : 215 - 219.
  • 8Pidin S, Mori T, Inoue K, et al. A novel strain en- hanced CMOS architecture using selectively deposited high tensile and high compressive silicon nitride films [ C]. In: Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International. 2004.
  • 9Fenouillet-Beranger C, Perreau P, Weber O, et al. En- hancement of devices performance of hybrid FDSOI/ bulk technology by using UTBOX sSOI substrates[ C]. In:VLSI Technology (VLSIT) , 2012 Symposium on. 2012. IEEE.
  • 10Yoshimi M, Cayrefourcq I, Mazur6 C. Strained-SOl (sSOI) technology for high-performance CMOSFETs in 45nm-or-below technology node [ C ]. In: Solid-State and Integrated Circuit Technology, 2006. ICSICTO6. 8th International Conference on. 2006. IEEE.

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功能材料与器件学报
2011年 第2期

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