摘要
为了校准相控阵雷达的接收信道,设计出一种基于DDS的弱信号源。采用单片机和FPGA控制DDS芯片AD9852产生脉冲线性调频与单频连续波信号,单片机的并口接口提供初始化DDS的寄存器设置,FPGA提供DDS的寄存器地址及控制信号,更主要的是提供时序控制脉冲触发信号源的输出和关断。结果表明,信号源可以输出幅度为-45 dBm、杂散优于70 dB的弱信号,完全满足校准相控阵雷达接收信道的性能要求,而且具有结构简单、可编程、可扩展、性能好、系统稳定及实用性强等优点。该设计同样适用于其他多信道接收工程。
In order to calibrate phased array radar, a weak signal generator which is based on DDS chip AD9852 is designed. This generator is controlled by a microcontroller and a FPGA chip, and can be used to generate chirp or single-tone signal. Microcontroller＇ parallel interface provided register configurations to initialize DDS. FPGA provided DDS address and control signals, as well as provided pulse to spring the generator on/off. Results show that the output amplitude of signal is under -45dBm, and stray is excelled 70 dB, it meets the requirements of calibration receiving system. Besides, this generator has some benefits including simple structure, programmable, good expandability, good and stable performance, good practicability and so on. This design suits muhireceiver engineering applications.
出处
《电子设计工程》
2011年第8期120-123,共4页
Electronic Design Engineering
