摘要
首先分析了8PSK的软解调原理,针对最优的对数似然比(LLR)运算复杂度较高的特点,选用了相对简化的最大值(MAX)算法作为可编程逻辑门阵列(FGPA)硬件平台实现方案。随后,通过QUARTUS II仿真平台对8PSK软解调器进行了硬件描述语言(VHDL)的设计实现和功能仿真,并通过与LDPC译码模块级联在Altera公司的Stratix II系列FPGA芯片上完成最终测试。通过与MATLAB仿真结果进行比较,验证上述简化8PSK软解调器设计的正确性和可行性。
In this paper,the principle of soft-decision demodulation for 8PSK is investigated,and the simplified Maximum（MAX） algorithm,for its low computational complexity,is selected for the implementation of field programmable gate array（FGPA） instead of the optimal Log Likelihood Ratio（LLR） algorithm.The Verilog hardware description language（VHDL） implementations and functional verifications for 8PSK soft demodulator are then carried out on the QUARTUS II platform.Then the final tests in combination with the LDPC decoder are conducted on the Altera Stratix II FPGA platform.By comparing with the MATLAB simulation results,the correctness and feasibility of the simplified 8PSK soft demodulator are verified.
出处
《通信技术》
2011年第2期45-47,共3页
Communications Technology
