期刊文献+

A low-power triple-mode sigma-delta DAC for reconfigurable(WCDMA/TD-SCDMA/GSM) transmitters 被引量:1

A low-power triple-mode sigma-delta DAC for reconfigurable(WCDMA/TD-SCDMA/GSM) transmitters
原文传递
导出
摘要 A sigma-delta (∑A) DAC with channel filtering for multi-standard wireless transmitters used in the software-defined-radio (SDR) system is presented. The conversion frequency, transfer function of the digital filter and the ∑A modulator, word-length of the IDAC and cut-off frequency of the analog reconstruction filter can be digitally programmed to satisfy specifications of WCDMA, TD-SCDMA and GSM standards. The ∑A DAC fabricated in SMIC 0.13μm CMOS process occupies a die area of 0.72 mm2, while consuming 5.52/4.82/3.04 mW in WCDMA/TD-SCDMA/GSM mode from a single 1.2-V supply voltage. The measured SFDR is 62.8/60.1/ 75.5 dB for WCDMA/TD-SCDMA/GSM mode, respectively. A sigma-delta (∑A) DAC with channel filtering for multi-standard wireless transmitters used in the software-defined-radio (SDR) system is presented. The conversion frequency, transfer function of the digital filter and the ∑A modulator, word-length of the IDAC and cut-off frequency of the analog reconstruction filter can be digitally programmed to satisfy specifications of WCDMA, TD-SCDMA and GSM standards. The ∑A DAC fabricated in SMIC 0.13μm CMOS process occupies a die area of 0.72 mm2, while consuming 5.52/4.82/3.04 mW in WCDMA/TD-SCDMA/GSM mode from a single 1.2-V supply voltage. The measured SFDR is 62.8/60.1/ 75.5 dB for WCDMA/TD-SCDMA/GSM mode, respectively.
出处 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2011年第2期96-101,共6页 半导体学报(英文版)
基金 Project supported by the National High Technology Research and Development Program of China(No.2009AA011605)
关键词 ∑A digital-to-analog converter LOW-POWER RECONFIGURABLE ∑A digital-to-analog converter low-power reconfigurable
  • 相关文献

参考文献8

  • 1Ghittori N, Vigna A, Malcovati P, et al. 1.2-V low-power multi- mode DAC+filter blocks for reconfigurable (WLAN/UMTS, WLAN/Bluetooth) transmitters. IEEE J Solid-State Circuits, 2006, 41(9): 1970.
  • 2Ghittori N, Vigna A, Malcovati P, et al. 1.2-V 30.4-dBm OIP3 re- configurable analog baseband channel for UMTS/WLAN trans- mitters. IEEE Trans Circuit Syst, 2006, 53(10): 2125.
  • 3Wang R. A multi-bit delta sigma audio digital-to-analog con- verter. PhD Thesis, Oregon State University, June 2006:14.
  • 4Pham J. Time-interleaved EA DAC for broadband wireless ap- plications. Master Thesis, University of Toronto, 2007.
  • 5Pelgrom M J M, Duinmaijer A C J, Welbers A P G. Matching properties of MOS transistors. IEEE J Solid-State Circuits, 1989, 24(5): 1433.
  • 6Baschirotto A, Ghittori N, Malcovati P, et al. Design trade-offs for a 10 bit, 80 MHz current steering digital-to-analog converter. The 2nd Annual IEEE Northeast Workshop on Circuits and Sys- tems, June 2004:249.
  • 7Cong Y, Geiger R L. Switching sequence optimization for gra- dient error compensation in thermometer-decoded DAC arrays. IEEE Trans Circuit Syst, 2000, 47(7): 585.
  • 8Mercer D A. Low-power approaches to high-speed current- steering digital-to-analog converters in 0.18μm CMOS. IEEE J Solid-State Circuits, 2007, 42(8): 1688.

同被引文献8

引证文献1

二级引证文献3

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部