摘要
本文介绍一种能够挂载于高速总线AHB的UART核。它充分利用了AMBA2.0协议对高速总线通信方式的规定,实现了慢速设备与高速总线的兼容。设计的一种自适应波特率发生器,通过对串行线路上的数据位进行精确周期采样计数,能够自动得出串行数据波特率;本设计同时在数据链路层实现了一个协议转换模块,通过规定协议的方式完成UART帧格式与AHB数据格式的相互转换,而协议中增加的自控信息,使得串行数据能够更快的转换成高速总线上的并行信号。该IP采用硬件描述语言(VHDL)设计,核心部件采用有限状态机(FSM)实现,最终形成可复用的IP软核。
The paper presents a UART IP core based on high-speed bus.It takes full advantage of the protocol of AMBA 2.0,while achieves the compatibility between low-speed and high-speed bus.By taking count of the period sampling for data bits of serial circuitry,a auto-tuning baud-rate generator can gain the baud-rate of serial data.Simultaneity,in order to transform the format between UART and AHB,the module for converting the protocol in the data link layer has been designed.In addition,with the accessorial self-control information,the core could transform the serial data into parallel signal in the high-speed bus.This IP is described by VHDL,whose hardcore is implemented with FSM（Finite State Machine）,and finally come into being a reusable soft core.
出处
《微计算机信息》
2011年第1期83-85,共3页
Control & Automation
