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小数运动估计在可重构处理器ReMAP的映射实现 被引量：2

Implementation of FME on Reconfigurable Processor ReMAP
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摘要 介绍一种在可重构媒体处理器ReMAP上实现小数运动估计的方法。ReMAP处理器由可重构的运算单元阵列和互联单元级联组成,具有高度可重构性和强大的并行计算能力。在ReMAP中映射实现了小数运动估计中的1/2插值、1/4插值和搜索等算法。通过算法的仿真验证分析,ReMAP可支撑小数运动估计的高性能实现,达到或接近ASIC的性能,并具有较好的应用灵活性,适于媒体处理应用。 A method to implement fractional motion estimation（FME） on ReMAP was presented.Consisting of reconfigurable processing element cascaded with interconnect element,the ReMAP is highly reconfigurable and powerful in parallel computation.Half-pixel interpolation and quarter-pixel estimation of fractional motion estimation were mapped on ReMAP,respectively.Mapping of the algorithm was simulated and verified,and the result was analyzed.It has been shown that,with the proposed method,high performance implementation equal to or near ASIC could be achieved on ReMAP.The proposed implementation method is adaptable to various applications,especially to media processing.
作者 张文良 雍珊珊 戴鹏 王新安 谢峥
机构地区 北京大学深圳研究生院集成微系统科学工程与应用重点实验室
出处 《微电子学》 CAS CSCD 北大核心 2011年第1期124-127,138,共5页 Microelectronics
关键词 H.264 小数运动估计 可重构处理器 H.264 Fractional motion estimation（FME） Reconfigurable processor
分类号 TN47 [电子电信—微电子学与固体电子学]
  • 相关文献

参考文献5

  • 1郑兆青,桑红石,赖晓玲,沈绪榜.一种新的用于H.264/AVC的运动估计VLSI结构[J].计算机学报,2007,30(12):2101-2108. 被引量：3
  • 2LIANG L, MCCANNY J V, SEZER S. Subpixel interpolation architecture for multistandard video motion estimation [J]. IEEE Trans Circ and Syst for Vid Technol, 2009, 19(12) : 1897-1901.
  • 3魏芳,李学明.基于MMX技术的H.264解码器优化[J].计算机工程与设计,2004,25(12):2218-2221. 被引量：6
  • 4YAI.CIN S, HAMZAOGLU I. A high performance hardware architecture for half-pixel accurate H. 264 motion estimation [C] // Int Conf Very Large Scale Integration. Nice, France. 2006: 63-67.
  • 5OKTEM S, HAMZAOGLU I. An efficient hardware architecture for quarter-pixel accurate H. 264 motion estimation [C]//10th Euromicro Conf Digit Syst Des Architec, Methods and Tools. Lubeck, Germany. 2007 :444-447.

二级参考文献17

  • 1王荣刚,李锦涛,黄晁,张勇东.一种分像素运动补偿插值滤波方法及高效VLSI实现[J].计算机学报,2005,28(12):2052-2058. 被引量：12
  • 2Wiegand T, Sullivan G H. 264 working draft number 2[EB/OL]. ftp://standards.pictel.com/video-site/0201_Gen/JVT-B118r8. doc.
  • 3Wiegand T, Sullivan G, Bjontegaard G, et al. Overview of H.264/AVC video coding standard[J]. IEEE Trans. circuits and systems for video technology, 2003, 13(7): 560-576.
  • 4H.264测试模型JM2.0[EB/OL].http://bs.hhi.de/～suehring/tml/download/jm20.zip.
  • 5Lappalainen V, Hallapuro A, Timo D H. Complexity of optimized H.26L video decoder implementation[J]. IEEE Trans. Circuits and Systems for Video Technology, 2003, 13(7): 717-925.
  • 6Lappalainen V, Hallapuro A, Timo D H. Optimization of emerging H.26L video encoder[C]. IEEE Workshop on Signal Processing Systems, 2001.406-415.
  • 7List P, Joch A, Lainema J, et al. Adaptive deblocking filter[J].IEEE Trans. Circuits and Systems for Video Technology, 2003, 13(7):614-619.
  • 8Malvar H S, Hallapuro A, Karczewicz M, et al. Low-complexity transform and quantization in H.264/AVC[J]. IEEE Trans. Circuits and Systems for Video Technology, 2003, 13(7):598 -603.
  • 9Sullivan G.. Recommended simulation common conditions for H.26L codingefficiency experiments on low-resolution progressive-scan source material [EB/OL]. ftp://standards.pictel. com/video-site/0109_San/VCEG-N81.doc.
  • 10Jiont Video Team. Draft ITU-T recommendation and final draft International standard of joint video specification. Geneva: ITU-T Rec H264 ISO/IEC 14496-10 AVC, 2003

共引文献7

同被引文献24

  • 1Khailany B, Dally W J, Kapasi U J, et al. Imagine media processing with streams [J]. IEEE Micro, 2001, 21 (2). 35-46.
  • 2Pham P, Mau P, Kim J, et al. An on-chip network fab- ric supporting coarse-grained processor array [ J]. IEEE transaction on Very Large Scale Integration (VLSI) Sys- tems, 2012, 21(1): 178-182.
  • 3Baumgarte V, Ehlers G, May F, et al. PACT XPP: a self-reconfigurable data processing architecture [ J]. The Journal of Supercomputing, 2003, 26(2): 167-184.
  • 4Singh H, Lee M H, Lu G, et al. MorphoSys: an inte- grated reconfigruable system for data-parallel and computa- tion-intensive applications [ J ]. IEEE Transactions on Computers, 2000, 49(5): 465-481.
  • 5Lattard D, Beigne E, Bernard C, et al. A telecom base- band circuit based on an asynchronous network-on-chip [ C]//IEEE International Solid-State Circuits Conference, Digest of Technical Papers. San Francisco (USA): IEEE Press, 2007: 258-601.
  • 6Vangal S, Howard J, Ruhl G, et al. An 80-tile 1.28 TFLPS network on-chip in 65 nm CMOS [ C ]//IEEE In- ternational Solid-State Circuits Conference, Digest of Tech- nical Papers. San Francisco (USA): IEEE Press, 2007 : 98-589.
  • 7Wentzlaff D, Griffin P, Hoffmann H, et al. On-chip in- terconnection architecture of the tile processor [J].IEEE Micro, 2007, 27 (5): 15-31.
  • 8Dai Peng, Wang Xin'an, Zhang Xing, et al. A high power efficiency reconfigurable processor for multimedia processing [ C ]// IEEE 8th International Conference on ASIC. Changsha (China): IEEE Press, 2009: 67-70.
  • 9Dai Peng, Wang Xin'an, Zhang Xing. A novel reconfigu- rable operator based IC design methodology for muhimedia processing [ C ]// 2009 IEEE Region 10 Conference (TENCON 2009). Singapore: IEEE Press, 2009 : 1-5.
  • 10Dai Peng, Wang Xin'an, Zhang Xing. Implementation of H. 264 algorithm on reconfigurable processor [ C ]// Asia Pacific Conference on Postgraduate Research in Mieroelec- tronics & Electronics (PrimeAsia 2009). Shanghai (Chi- na) : IEEE Press, 2009: 237-240.

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微电子学
2011年 第1期

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