摘要
基于0.5μm标准CMOS工艺,利用折叠式共源共栅电路和简单放大器级联结构,设计了一种增益高、建立时间短、稳定性好和电源抑制比高的低压CMOS运算放大器。用CadenceSpectre对电路进行优化设计,整个电路在3.3 V工作电压下进行仿真,其直流开环增益100.1dB,相位裕度59°,单位增益带宽10.1 MHz,建立时间1.06μs。版图面积为410μm×360μm。测试结果验证了该运算放大器电路适用于电源管理芯片。
Based on 0.5 μm standard CMOS technology,a low voltage CMOS operational amplifier with high gain,short settling time,good stability and high PSRR was designed using a folded-cascode circuit and a simple cascade structure.The circuit was optimized and simulated with Spectre of Cadence.Results showed that the amplifier had an open-loop gain of 100.1 dB,a phase margin of 59°,a unity gain bandwidth of 10.1 MHz and a settling time of 1.06 μs at 3.3 V power supply.The chip occupies an area of 410 μm×360 μm.Test results indicated that the proposed operational amplifier is applicable for power management IC.
出处
《微电子学》
CAS
CSCD
北大核心
2011年第1期19-22,共4页
Microelectronics
基金
甘肃省科技支撑计划项目(097GKCA052)
兰州市科技发展计划项目(2009-1-1)
