摘要
高精度流水线ADC的设计需要校准技术来提高其转换精度.基于统计的数字后台校准方法无需校准信号,直接通过对输出的统计得到误差值的大小,将其从数字输出中移除从而消除了ADC输出非线性.将该校准方法应用于14bit流水线ADC中,仿真结果表明校准后信噪失真比SNR为76.9dB,无杂散动态范围SFDR为73.9dB,有效精度ENOB从9bit提高到12.5bit.
Pipelined ADCs with high resolution need calibration technique to increase their conversion precision.The statistical-based digital background calibration technique presented here calculates the output error via statistic analysis,and then the error is subtracted from the ADC output.With this calibration architecture used in a 14-bit pipelined ADC,the simulation results show that after calibration the SNR is 76.9 dB,SFDR is 73.9 dB,and the ENOB is improved from 9 bit to 12.5 bit.
出处
《微电子学与计算机》
CSCD
北大核心
2011年第2期69-73,共5页
Microelectronics & Computer
基金
总装预研基金项目(9140A08020507)
关键词
流水线ADC
数字后台校准
电容失配
运放有限增益
pipelined ADC
digital background calibration
capacitor mismatch
finite op-amp gain
