摘要
根据VME总线接口规范和协议要求,应用CPLD芯片和VHDL语言,进行了VME总线地址译码、数据读写及中断控制接口逻辑功能设计,完成了电路板研制和功能测试,试验研究表明其满足要求,所提出的设计思路方法合理可行.
A kind of VMEbus logic interface circuitry,which mainly deals with address coding,data read-writing and interrupt requesting,is developped with CPLD element and by use of VHDL language.The functional experiment based on a VMEbus computer system is completed,in which the circuitry is used as channels for signal input and output.The experiment result shows that the circuitry achieves the expected functions and the design method is reasonable.
出处
《机械与电子》
2010年第12期18-21,共4页
Machinery & Electronics
