摘要
设计了一种适用于导航系统的低功耗、串行维特比译码器电路.介绍了设计的维特比译码器电路的整体结构和各部分硬件电路的设计与特点,仿真结果显示设计的维特比译码器电路能够正常译码,并能纠正传输过程中的错误比特;SMIC0.18μm工艺下的综合结果表明译码器电路的面积只有4102门,功耗为399.514μW.
We designed low power serial Viterbi decoder used in navigation systems.We introduce the whole architecture of the decoder and the design and features of each module in detail.The waveform shows that the designed Viterbi decoder can work in right condition and correct errors during transmission.The synthesize result under SMIC 0.18 μm technology shows that the area of the circuit is 4 102 gates,and the power is 399.514 μW.
出处
《微电子学与计算机》
CSCD
北大核心
2011年第1期54-57,60,共5页
Microelectronics & Computer
