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锁相环中克服非理想因素的鉴相器和电荷泵设计 被引量：2

Design of Phase-Frequency Detector and Charge Pumpin Phase-Locked Loops with Nonideal Factors
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摘要 讨论了锁相环中鉴相器和电荷泵中非理想因素及其克服方法。电路设计采用SMIC0.18μm CMOS工艺和Cadence Spectre仿真器。通过在重置反馈路径上加入延迟单元的方法来消除鉴相器的死区。比较了两种传统电荷泵电路的设计方法,通过加入ReplicaBias电路和单位增益运放,实现了上下电流的高匹配性。 The nonideal factor of the phase-frequency detector and charge pump in phase-locked loop and its overcome method are proposed.The whole circuit is implemented with the SMIC 0.18 μm CMOS technology and the simulator of Cadence Spectre.The dead zone of the PFD is eliminated by adding delay cells in the reset path.Two tradition charge pump design methods are compared.The charge pump circuit proposed here incorporates the replica bias circuit and unit gain operation amplifier simultaneously with the output current accurate matching.
作者 程知群 朱雪芳 周云芳 高俊君 徐胜军
机构地区 杭州电子科技大学射频电路与系统教育部重点实验室
出处 《电子器件》 CAS 2010年第4期442-446,共5页 Chinese Journal of Electron Devices
基金 国家自然科学基金资助项目(60776052)
关键词 鉴相器 鉴相死区 电荷泵 高电流匹配 phase-frequency detector dead zone charge pump accurate current matching
分类号 TN4 [电子电信—微电子学与固体电子学]
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参考文献10

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同被引文献16

  • 1Wang Ping-Ying, Zhan Jing-Hong Conan, Chang Hsiang-Hui, et al. A Digital Intensive Fractional-N PLL and All-Digital Self- Calibration Schemes [ J ]. IEEE Journal of Solid-State Circuits, 2009,44 (8) :2182-2192.
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  • 3Wu Chia-Tsun, Shen Wen-Chang, Wang Wei, et al. A Two-Cycle Lock-in Time ADPLL Design Based on a Frequency Estimation Algorithm[J]. IEEE Trans. Circuits Syst. ]I,2010,57(6) :430-434.
  • 4Xu Liangge, Karl Stadius, Jussi Ryynanen. An All-Digital PLL Frequency Synthesizer with an Improved Phase Digitization Approach and an Optimized Frequency Calibration Technique [ J ]. IEEE Trans. Circuits Syst. 1,2012,59 (12) : 1 - 14.
  • 5张酷元,朱劲.一种新型数字锁相环的建模和实现[J].电子技术研发,2010(6):19-21.
  • 6周郭飞,苏厉,金德鹏,等.基于Vefilog-A数控Lc振荡器系统的行为级建模[J].集成电路设计与开发,2009,34(4):375-380.
  • 7Ihor Harasymiv, Manfred Dietrich, Uwe Knochel. Fast Mixed-Mode PLL Simulation Using Behavioral Baseband Models of Voltage- Controlled Oscillators and Frequency Dividers [ C ]//SM2ACD, 2010 : 1-6.
  • 8Jingchang Nan, Jianwei Ren, Mifang Cong, et al. Design of PLL Be- havioral Model Based on the Verilog-A[ C1//2011:380-383.
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电子器件
2010年 第4期

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