摘要
数字锁相环(DPLL)技术在数字通信、无线电电子学等众多领域得到了极为广泛的应用,利用DPLL可以从串行位流数据中恢复出接收位同步时钟。时钟数据恢复(CDR)电路是同步光纤系统中的核心部件,性能优越的锁相环电路对CDR电路的实现有着极其关键的作用。本文介绍了一种全数字化CDR电路的设计。仿真和实验测试结果表明,该CDR电路可以对相位变化快速同步,尤其对突发数据的时钟恢复,相位抖动的消除有效。
DPLL is extensively used in digital communication, wireless electronics and kinds of other domain. Bit synchronization clock can be recovered from serial bit streams data by DPLL. So a DPLL with prime performance has rather pivotal action for implementation of the synchronous optical systems, especially in CDR circuit . A CDR circuit design is introduced in this paper. The CDR circuit is realized by DPLL. Simulation and practical test illustrate, this CDR can fast synchronize with phase variation and effectively remove phase jitter, especially for the clock recovery of the burst data..
出处
《科技信息》
2010年第01X期74-75,共2页
Science & Technology Information
关键词
数字锁相环
时钟数据恢复
同步
FPGA
Digital phase locked loop （DPLL）
Clock and data recovery（ CDR）
Synchronization
FPGA
