摘要
提出了一种容量可变的嵌入式同步ＳＲＡＭ。通过采用存储阵列的分块、敏感放大器的分级等技术，对电路的结构进行了优化。着重讨论了存储阵列的分块原则，分析了分块的字长、字数对电路的面积、速度、功耗等因素的影响。采用０．６－μｍＣＭＯＳ工艺，容量为２ｋ×１６ｂｉｔ的ＳＲＡＭ可工作在１００ＭＨｚ的频率下，芯片面积为２．５３ｍｍ×２．７５ｍｍ，平均功耗为４．７ｍＷ／ＭＨｚ。
A set of embedded synchronous CMOS SRAM with configurable capacity is presented.A divided memory cell array architecture and high speed hierarchical sense amplifiers are employed in the design to optimize the structure of the circuit.The principle of dividing the memory cell array and the trade off between area,speed and power are discussed.A 2 k×16bit SRAM having a chip area of 2.53 mm × 2.75 mm is fabricated using 0.6 μm CMOS technology.The device operates at 100 MHz with a 5 V supply and its average power dissipation is 4.7 mW /MHz.
出处
《微电子学》
CAS
CSCD
北大核心
1999年第3期194-199,共6页
Microelectronics
