摘要
A 12-bit intrinsic accuracy digital-to-analog converter integrated into standard digital 0.18μm CMOS technology is proposed. It is based on a current steering segmented 6＋6 architecture and requires no calibration. By dividing one most significant bit unary source into 16 elements located in 16 separated regions of the array, the linear gradient errors and quadratic errors can be averaged and eliminated effectively. A novel static performance testing method is proposed. The measured differential nonlinearity and integral nonlinearity are 0.42 and 0.39 least significant bit, respectively. For 12-bit resolution, the converter reaches an update rate of 100 MS/s. The chip operates from a single 1.8 V voltage supply, and the core die area is 0.28 mm^2.
A 12-bit intrinsic accuracy digital-to-analog converter integrated into standard digital 0.18μm CMOS technology is proposed. It is based on a current steering segmented 6＋6 architecture and requires no calibration. By dividing one most significant bit unary source into 16 elements located in 16 separated regions of the array, the linear gradient errors and quadratic errors can be averaged and eliminated effectively. A novel static performance testing method is proposed. The measured differential nonlinearity and integral nonlinearity are 0.42 and 0.39 least significant bit, respectively. For 12-bit resolution, the converter reaches an update rate of 100 MS/s. The chip operates from a single 1.8 V voltage supply, and the core die area is 0.28 mm^2.
基金
Project supported by the National High Technology Research and Development Program of China(No.2008AA010700)
