摘要
A novel structure of a phase-locked loop （PLL） characterized by a short locking time and low jitter is presented, which is realized by generating a linear slope charge pump current dependent on monitoring the output of the phase frequency detector （PFD） to implement adaptive bandwidth control. This improved PLL is created by utilizing a fast start-up circuit and a slope current control on a conventional charge pump PLL. First, the fast start-up circuit is enabled to achieve fast pre-charging to the loop filter. Then, when the output pulse of the PFD is larger than a minimum value, the charge pump current is increased linearly by the slope current control to ensure a shorter locking time and a lower jitter. Additionally, temperature variation is attenuated with the temperature compensation in the charge pump current design. The proposed PLL has been fabricated in a kind of DSP chip based on a 0.35 μm CMOS process. Comparing the characteristics with the classical PLL, the proposed PLL shows that it can reduce the locking time by 60% with a low peak-to-peak jitter of 0.3% at a wide operation temperature range.
A novel structure of a phase-locked loop （PLL） characterized by a short locking time and low jitter is presented, which is realized by generating a linear slope charge pump current dependent on monitoring the output of the phase frequency detector （PFD） to implement adaptive bandwidth control. This improved PLL is created by utilizing a fast start-up circuit and a slope current control on a conventional charge pump PLL. First, the fast start-up circuit is enabled to achieve fast pre-charging to the loop filter. Then, when the output pulse of the PFD is larger than a minimum value, the charge pump current is increased linearly by the slope current control to ensure a shorter locking time and a lower jitter. Additionally, temperature variation is attenuated with the temperature compensation in the charge pump current design. The proposed PLL has been fabricated in a kind of DSP chip based on a 0.35 μm CMOS process. Comparing the characteristics with the classical PLL, the proposed PLL shows that it can reduce the locking time by 60% with a low peak-to-peak jitter of 0.3% at a wide operation temperature range.
基金
Project supported by the National Defense Pre-Research Project of China(No.51308010610)
