摘要
采用TSMC0.35μm工艺参数,基于多输出端第二代电流传输器(MOCCⅡ)提出了一种新型CCⅢ电路,电路采用轨对轨的输入结构,有效地提高了信号摆幅;通过电路内部晶体管提供偏置,达到了减少芯片面积和降低功耗的目的。HSPICE仿真结果表明,在±1 V供电电压下,该CCⅢ的电压跟随误差为0.06 dB,-3 dB带宽为434.3 MHz;端口Y与X之间的电流跟随误差为0.06 dB,-3 dB带宽为381.2 MHz;端口Z+与X之间的电流跟随误差为0.02 dB,-3 dB带宽为334.1 MHz;端口Z-与X之间的电流跟随误差为0.05 dB,-3 dB带宽为665.8 MHz;整体电路的功耗为2.133 mW。据CCⅢ电路设计了一种电流模式带通二阶滤波器,结果与理论值较吻合。
A novel CMOS third generation current conveyor （CCIII） with a ＋ 1 V power supply based on muh-output CCII （MOCCII） is presented. It adopts the rail-to-ruil input structure to improve the signal swing. Thanks to its self-bias circuit, the proposed CCIII reduces chip areas and power consumption. The results of HSPICE simulation based on TSMC＇s 0.35 ~m technology show that the CCIII has a voltage transfer error of 0.06 dB with - 3 dB frequency bandwidth of about 434.3 MHz. The current transfer error between terminal Y with terminal X is 0.06 dB with -3 dB frequency bandwidth of about 381.2 MHz. The current transfer error between terminal Z ＋ with terminal X is 0.02 dB with - 3 dB frequency bandwidth of about 334.1 MHz. The current transfer error between terminal Z - with terminal X is 0.05 dB with -3 dB frequency bandwidth of about 665.8 MHz. The power consumption is only 2. 133 mW. The applications of the CCIII to realize current model second-order bandpass filter are given.
出处
《半导体技术》
CAS
CSCD
北大核心
2010年第9期913-917,共5页
Semiconductor Technology
基金
国家自然科学基金资助项目(60572026)
四川省学术与技术带头人培养基金重点资助项目(Q024131103010018)
西南交通大学科技发展基金(2006A05)
