期刊文献+

树拓扑片上网络的低能耗映射

Low Energy Mapping for Tree Based Networks-on-Chip
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摘要 针对树拓扑片上网络(NoC)中通信时延受约束的低能耗映射问题,提出了一种递归的二路划分算法RPM(recursive bipartitioning for mapping)。RPM基于分而治之策略,首先将NoC映射转化为多层次的IP核通信任务图划分问题,并采用带参数的Kernighan-Lin算法实现最小割值划分。实验结果表明,与已有算法相比,RPM可以在较短的时间内获得能耗更低的映射解。通过设置不同的参数,RPM既可以用于生成高质量的优化解,也可用于快速的NoC设计空间探索中。 A recursive bipartitioning algorithm, RPM, is proposed for low energy mapping in tree-based Network-on-Chip (Not) architectures subject to communication latency constraints. The mapping problem is formulated to multi-level IP core communication task graph partitioning problems, and the modified Kernighan-Lin mincut heuristic is used to solve them. Experimental results show that RPM obtains lower energy mapping solutions compared with existing algorithms.
出处 《电子科技大学学报》 EI CAS CSCD 北大核心 2010年第4期607-611,共5页 Journal of University of Electronic Science and Technology of China
基金 国家863项目(2006AA01Z173 2007AA01Z131)
关键词 二路划分 能耗优化 映射 片上网络 树拓扑 bipartitioning energy optimization mapping networks-on-chip tree based topology
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参考文献12

  • 1ATIENZA D, ANGIOLINI F, MURALI S, et al. Network -on-chip design and synthesis outlook[J]. Integration, the VLSI Journal, 2008, 41(3): 340-359.
  • 2MARCON C AM, MORENO E I, CALAZAblS N L V, et al. Comparison of network-on-chip mapping algorithms targeting low energy consumption[J]. IET Computers & Digital Techniques, 2008, 2(6): 471-482.
  • 3HU J, MARCULESCU R. Energy-aware mapping for tUe-based NoC architectures under performance constraints [C]//Proceedings of the Conference on Asia South Pacific Design Automation. New York, USA: ACM Press, 2003: 233- 239.
  • 4MARCON C AM, MORENO E I, CALAZANS N L V, et al. Comparison of network-on-chip mapping algorithms targeting low energy consumption[J], lET Computers & Digital Techniques, 2008, 2(6): 471-482.
  • 5杨盛光,李丽,高明伦,张宇昂.面向能耗和延时的NoC映射方法[J].电子学报,2008,36(5):937-942. 被引量:46
  • 6常政威,谢晓娜,桑楠,熊光泽.片上网络映射问题的改进禁忌搜索算法[J].计算机辅助设计与图形学学报,2008,20(2):155-160. 被引量:16
  • 7GRECU C, JONES M. Performance evaluation and design trade-offs for network-on-chip interconnect architectures[J]. IEEE Transactions on Computers, 2005, 54(8): 1025-1040.
  • 8CHANG K C, CHEN T E Low-power algorithm for automatic topology generation for application-specific networks on chips[J]. IET Computers & Digital Techniques, 2008, 2(3): 239-249.
  • 9GUERRIER P, GREINER A. A generic architecture for on-chip packet-switched interconnections[C]//Proceedings of the Conference on Design, Automation and Test in Europe. Washington, D C, USA: IEEE Compater Society, 2000: 250- 256.
  • 10HOLLSTEIN T, GLESNER M. Advanced hardware/ soRware co-design on reconfigurable network-on-chip based hyper-platforms[J]. Computers & Electrical Engineering, 2007, 33(4): 310-319.

二级参考文献35

  • 1周干民,尹勇生,胡永华,高明伦.基于蚁群优化算法的NoC映射[J].计算机工程与应用,2005,41(18):7-10. 被引量:14
  • 2高明伦,杜高明.NoC:下一代集成电路主流设计技术[J].微电子学,2006,36(4):461-466. 被引量:32
  • 3吴春明,陈治,姜明.蚁群算法中系统初始化及系统参数的研究[J].电子学报,2006,34(8):1530-1533. 被引量:48
  • 4张磊,李华伟,李晓维.用于片上网络的容错通信算法[J].计算机辅助设计与图形学学报,2007,19(4):508-514. 被引量:18
  • 5Bjerregaard T, Mahadevan S. A survey of research and practices of network-on-chip [J]. ACM Computing Surveys, 2006, 38 (1): 1-51
  • 6Ogras U Y, Hu J, Mareuleseu R. Key research problems in NoC design: a holistic perspective [C]//Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, Jersey City, 2005 : 69 -74
  • 7Murali S, De Micheli G. Bandwidth-constrained mapping of cores onto NoC architectures [C] //Proceedings of Design, Automation and Test in Europe Conference and Exhibition, Paris, 2004: 896- 901
  • 8Ascia G, Catania V, Palesi M. Multi-objective mapping for mesh-based NoC architectures [C] //Proceedings of the 2nd IEEE/ACM/IFIP International Conference Hardware/Software Codesign and System Synthesis, Stockholm, 2004: 182-187
  • 9Hu J, Marculescu R. Energy-aware mapping for tile-based NoC architectures under performance constraints [ C] //Proceedings of Asia South Pacific Design Automation Conference, Kitakyushu, 2003 : 233-239
  • 10Lei T, Kumar S. A two-step genetic algorithm for mapping task graphs to a network on chip architecture [C] //Proceedings of the Euromicro Symposium on Digital Systems Design, Belek, Turkey, 2003:180-187

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