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不恢复余数阵列除法器的FPGA实现

FPGA Implementation About the Array Divider on the Addition and Subtraction Alternating Method
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摘要 在研究不恢复余数法的算法基础上,阐述以可控加/减法器(CAS)为基本组成单元的阵列除法器的构造原理,并给出一个完整的定点小数补码除法逻辑图,最后提出一种基于现场可编程门阵列(Field-Programmable Gate Array,简称FPGA)的除法器的硬件实现方法. The paper based on the algorithm about addition and subtraction alternating method,described in order to CAS as the basic unit of the structure array divider principle,and gave a full complement of fixed-point decimal division logic diagram.Finally,the paper presented a FPGA-based hardware implementation of the divider.
作者 吉雪芸 朱有产
机构地区 华北电力大学信息与网络管理中心
出处 《保定学院学报》 2010年第3期56-59,共4页 Journal of Baoding University
关键词 CAS 不恢复余数法 并行除法 阵列除法器 FPGA CAS addition and subtraction alternating method parallel division array divider FPGA
分类号 TP391.41 [自动化与计算机技术—计算机应用技术]
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保定学院学报
2010年 第3期

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