摘要
为了满足某测控平台的设计要求,设计并实现了基于FPGA的六通道HDLC并行通信系统。该系统以FPGA为核心,包括FPGA、DSP、485转换接口等部分。给出了系统的电路设计、关键模块及软件流程图。测试结果表明,系统通讯速度为1Mb/s,并且工作稳定,目前该设计已经成功应用于某样机中。
In order to meet the specific requirement and Control platform, a 6 channel HDLC protocol parallel communication system is designed and implemented. The system using FPGA, DSP and 485 convert interface. The design scheme flowchart, as well as the realization of key module arc presented. The system is tested by PC with PCI interface, experiments resuhs show that the interface works stable with 1 Mb/s speed. The design has been successfully applied in some sample products.
出处
《电子技术应用》
北大核心
2010年第5期97-99,共3页
Application of Electronic Technique
