摘要
数字三相锁相环中含有大量乘法运算和三角函数运算,占用大量的硬件逻辑资源。为此,提出一种数字三相锁相环的优化实现方案,利用乘法模块复用和CORDIC算法实现三角函数运算,并用VerilogHDL硬件描述语言对优化前后的算法进行了编码实现。仿真和实验结果表明,优化后的数字三相锁相环大大节省了FPGA的资源,并能快速、准确地锁定相位,具有良好的性能。
There are many muhiplication operations and trigonometric function operations based two phase rotational coordinates in digital implementation of the three phase-locked loop, which will occupy too much hardware resouree. An optimized scheme which reuses multiplication and uses CO1RD1C algorithm is proposed in this paper. The un-optimized digital three phase-locked loop and the optimized digital three phase-locked loop are both implemented by Verilog HDL. The results of the simulation and the experiment verify the proposed digital three phase-locked loop could reduce the use of the source of the FPGA and lock the phase rapidly and accurately.
出处
《电子技术应用》
北大核心
2010年第5期63-65,69,共4页
Application of Electronic Technique
