摘要
介绍了一种应用于数字通信系统中的新型位同步电路的设计方案,并通过硬件实现了此方案。该方案有效解决了传统位同步提取方法中的一些问题,如电路实现和技术过于复杂的问题、相位模糊、影响系统性能等。电路设计用同系列数字化芯片硬件实现后电路简单稳定,干扰小,同步精度高,跟踪范围比较宽,输入主频低,最后给出了仿真结果和硬件性能测试数据。
This paper describes a novel design of synchronization circuit applied in digital communication systems.The design program effectively solves a number of problems in the conventional bit synchronization extraction methods,such as that the circuit implementation and technology are too complex,the phase ambiguous,and the system performance is affected.Circuit design is realized through hardware circuits with digtal chip in homologous series,and thus the circuit is high in stability,little in interference,accurate in synchronization,wide in tracking range and low in input master frequency.Finally,the performance test data and the hardware simulation results are given.
出处
《通信技术》
2010年第4期40-42,共3页
Communications Technology
关键词
数字通信
位同步
硬件实现
digital communication
bit synchronization
hardware realization
