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面向视频处理的粗粒度可重构单元设计 被引量：1

Design of a Coarse-grain Reconfigurable Cell for Video Processing
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摘要 针对视频处理算法,设计了一种面向视频处理的粗粒度可重构处理单元.它可以执行8位数据的加法、减法、乘法、乘加和求两数差的绝对值等操作,可以有效地支持高计算密度的视频处理算法.可重构处理单元使用Verilog设计,采用CMOS0.18μm工艺DC综合,面积为97913μm,关键路径为4.51ns,总的动态功耗为4.2mW.完成一次8×8像素块的2D-DCT算法和全搜索块匹配MAD算法分别需要10和15个时钟周期. This paper presents VORC（Video Oriented Reconfigurable Cell）,a coarse-grain reconfigurable cell optimized for video processing. The cell has been designed to provide a dense support for video processing 8-bit arithmetic operations such as addition,subtraction,multiplication,multiply-accumulation and absolute value of the difference. The cell has been descripted with verilog and synthsized under 0.18μm COMS proces with Synopsys Design Compiler. The area is 97 913μm2 and the critical path is 4.51nm and the total dynamic power is 4.2mW. The entire 8×8 2D-DCT and FSBM MAD respectively require 10 and 15 cycles.
作者 赵启林 李冰 时美强 熊军
机构地区 东南大学集成电路学院
出处 《微电子学与计算机》 CSCD 北大核心 2010年第5期82-86,共5页 Microelectronics & Computer
关键词 可重构处理单元 视频压缩编码 并行计算 reconfigurable processing cell video compression parallel computation
分类号 TN402 [电子电信—微电子学与固体电子学]
  • 相关文献

参考文献8

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共引文献7

同被引文献7

  • 1葛晨阳,王东,孙宏滨,张超,张斌.一种可重构的数字视频处理SoC芯片验证平台[J].微电子学与计算机,2009,26(2):62-65. 被引量：5
  • 2Compton L, Hauck S. Reconfigurable computing: a survey of systems and software[J]. ACM Computing Surveys, 2002, 34 (2): 171-210.
  • 3Singh H, Lee Ming-Hau, Lu Guangming, et al. Mor- phoSys: an integrated reconfigurable system for data- parallel and compute intensive applications[J]. IEEE Trans on Computer, 2000, 49 (5): 465-481.
  • 4Cao Liang, Huang Xinming. SmartCelh an energy ef- ficient coarse-grained reconfigurable architecture for stream-based applications [J]. EURASIP Journal on Embedded Systems, 2009(15) :231-234.
  • 5Ansaloni G, Bonzini P, Pozzi L. Design and architec- tural exploration of expression-grained reconfigurable arrays[C]///Proc of the 2008 Symposium on Applica- tion Specific Processors. California, 2008:26-33.
  • 6Gong Danian, He Yun, Cao Zhigang. New cost-effec- tive VLSI Imp oementation of a 2-D discrete cosine transform and its onverse[J]. IEEE Trans on Circuits and Systems for Video Technology, 2004, 14(4) :405- 415.
  • 7潘鹏,王鹏,林水生.可重构处理器阵列的系统级建模研究[J].微电子学与计算机,2011,28(11):85-88. 被引量：3

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微电子学与计算机
2010年 第5期

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