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低功耗低误码率的传感器网络节点芯片数字基带设计 被引量:3

A Low Power Low BER Digital Baseband Design for WSN SoC
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摘要 本文针对无线传感器网络节点片上系统特点和需求,研究一种低功耗、高性能、低误码率的数字基带(Easibaseband),提出了一种复用加法器和乘法器的设计方法,实现了匹配滤波器,可节省硬件资源并提高系统性能;提出了一种自适应门限的自动增益控制方法,可配合软硬件协同的工作方式,节省接收机的功耗;提出了采用自适应门限的施密特触发器方式进行信号相位判决的方法,降低了解调误码率.本设计在Xilinx的Spartan-3E FPGA上验证并实现,测试结果表明,本收发机的数据传输率可达到111kb/s并支持ISM24GHz频段的射频芯片,比传统的并行滤波器节省了5/6的硬件资源,比不采用自动增益控制节省了10.8%的接收机功耗,在信噪比13dB时,误码率在10-4以下,远低于WiseNET的接收误码率. We have developed a low power and low bit error rate (BER) digital baseband as a part of wireless sensor net- work node system-on-a-chip (SoC),namely Easibaseband..An automatic gain conlrol (AGC) module has been proposed based on hardware and software co-design which can save the power consumption of receiver up to 10.8% .It also realizes a digital matched filter (DMF) in receiver to reduce the BER.A phase synchronization algorithm is also proposed. The transceiver utilizes FSK modu- lation encoder in baseband at a data rate of 111 kb/s in the 2.4GHz ISM band to provide wireless connectivity between two sensor nodes. The design has been validated in Spartan-3E FPGA. The results showed that the proposed schemes achieve better performance than existing work.
出处 《电子学报》 EI CAS CSCD 北大核心 2010年第B02期123-127,共5页 Acta Electronica Sinica
基金 国家863高技术研究发展计划(No.2007AA01Z2A9) 国家973重点基础研究发展规划(No.2006CB303000)
关键词 无线传感器网络节点 片上系统 数字基带 自动增益控制 位同步 匹配滤波器 软硬件协同 wireless sensor network node system on a chip (SoC) digital baseband automatic gain control (AGC) phase synchronization digital matched filter (DMF) software and hardware co-operation
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参考文献8

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