摘要
采用行列分解法实现了二维DCT变换,其一维DCT采用Loeffler算法结构,结合位宽优化与CSD乘法优化,在FPGA芯片上无内嵌硬件乘法器情况下,一维DCT计算模块仅需要1504LUTs;有内嵌硬件乘法器情况下,仅需要688LUTs与22个内嵌9*9乘法器。将二维DCT计算模块封装为wishbone接口的IP核,在AlteraDE2-70开发板上实测二维DCT计算速度是软件快速DCT算法的296倍,可应用于JPEG图像处理、音频处理等场合。
A 2-D DCT IP core was designed based on the row column decomposition Method,and the 1-D DCT was implemented based on Loeffler＇s fast DCT algorithm.By use of bit-width optimization and CSD multiplier optimization,the 1-D DCT module only used 1504 LUTs without embedded hardware multipliers,or 688 LUTs and 22 embedded hardware multipliers on FPGA.The 2-D DCT module core was encapsulated with wishbone bus,and the IP core is 296 times faster than software 2-D DCT calculation,and cab be used on JPEG image processing or audio processing.
出处
《微计算机信息》
2010年第14期23-25,共3页
Control & Automation
基金
山东科技大学春蕾计划资助
