摘要
如何提升处理器本身的容错性能,使其能够更好地应用于各种复杂多变的环境,已经成为当前研究的热点;对于这一问题,可以将故障屏蔽技术(三模块冗余,校正器)和故障恢复技术(多数表决恢复,检查点)综合应用到处理器的容错设计中;以VHDL代码实现的8051处理器为研究对象,综合采用上述方法设计容错处理器,并在仿真环境下采用故障注入的方法对其容错性能进行测试和验证;研究表明采用这些技术可以构造具有良好可信性和稳定性的容错处理器。
It has become a research focus that how to enhance the fault-tolerant performance of processor, so that it can be better applied to a variety of complex and changing environment. For this problem, fault shielding technology （Triple Modular Redundancy, Correetor） and fault recovery technology （Majority voting, Checkpoint） can be applied. This paper chooses 8051 processor achieved by VHDL as the research object, in order to design a fault-tolerant processor using those techniques above-mentioned. The fault-tolerance of this processor is tested and validated by the way of fault injection and the conclusion shows that a fault- tolerant processor with high ability of creditability and stability is achieved.
出处
《计算机测量与控制》
CSCD
北大核心
2010年第4期892-895,共4页
Computer Measurement &Control
基金
航空科学基金(2008ZD53035)
陕西省自然科学基金(SJ08F20)资助
关键词
处理器
容错
三模块冗余
校正器
检查点
processors
fault-tolerance
triple modular redundancy
corrector
checkpoint
