摘要
小波变换以其优越的性能得到了越来广泛的应用，但是目前在处理器中对小波算法的支持．主要采用专门的硬件加速部件完成，这样即增加了设计开销，也不利于应用的扩展。而随着集成电路工艺的不断发展，在单片处理器的体系结构级考虑对小波的支持已经成为可能。该文就是基于这样的一种观点，通过分析9／7提升小波变换以及9／7整形小波变换在核心操作，数据流．并行性等方面的特点，提出了在处理器级支持小波变换的体系结构设计.
Wavelet transform with its superior performance has been more and more widely applied. But recent support of the wavelet algorithm in the processor, is mainly completed by the specialized accelerating completion in the hardware, which increases the design costs and is not conducive to the expansion of its applications. However, with the development of IC technique, consideration to support wavelet transform by architecture-level in the processor of MCU has been possible. On the basis of such a view, the paper analyzes the features of 9/7 lifting wavelet transform and 9/7 integer wavelet transform in the core operations, data flow, and parallelism, etc. It puts forward the architecture design to support wavelet transform in processor class.
作者
欧阳玲
OU Yang-ling （Hunan Normal University, Changsha 410081, China）
出处
《电脑知识与技术》
2010年第4期2529-2530,共2页
Computer Knowledge and Technology
关键词
小波变换
处理器
体系结构
算法
wavelet transform
processor
architecture
algorithm
