摘要
为了利用片上缓冲技术来提高处理器应用性能,提出一种面向写穿透Cache的写合并设计方法.使用同步动态随机存储器(SDRAM)的单个写方式和片上写缓冲器,对SDRAM一行内的局部数据采用写合并策略,由此提高了外部存储的访问效率,同时给出了连续和单个Cache读写的缓存与内存的数据一致性策略.在寄存器传输语言(RTL)仿真环境下使用mp3解码对Leon2处理器进行数据测试,结果表明:在缓冲区优化为3行8列的参数下,SDRAM每次行开启平均进行7.8个字的写入操作,外存的读写效率由12%提高到19%;在TSMC0.18μm工艺下,综合后面积为0.263mm2,流片后工作主频为100MHz.
A write coalescing design for write-through cache is proposed to promote the performance of application processors using on-chip buffer. The scheme of write coalition for the local data in the same row of SDRAM （synchronous dynamic random access memory） is designed to improve accessing efficiency by employing the single write mode of SDRAM and on-chip buffer. A coherence scheme for the single or multiple cache data reading or writing is also presented. Simulation for mp3 decoding data is implemented in the RTL （register transmit language） simulation environment for Leon2 processor. The simulation results show that when the on-chip buffers are optimized at 3 rows and 8 columns, average 7.8 words are written into the SDRAM after every row pre-charge, and the accessing efficiency increases from 12% to 19% at 100 MHz, and that the area of the proposed design is 0. 263 mm^2 under TSMC 0. 18μm process.
出处
《西安交通大学学报》
EI
CAS
CSCD
北大核心
2010年第4期1-4,共4页
Journal of Xi'an Jiaotong University
基金
国家自然科学青年基金资助项目(60905007)
国家高技术研究发展计划资助项目(2009AA01Z307
2009AA011709)
关键词
写穿透
写合并
处理器
同步读写存储器
读写效率
write through
write coalescing
memory
access efficiency processor
synchronous dynamic random access
