摘要
介绍了将数字正交解调算法应用于CPT原子钟系统的锁相环路，通过FPGA硬件结构实现解调功能所开展的研究。经MATLAB和QUARTUS2的联合仿真表明，该算法抗噪声能力强，解调结果可靠性高，是应用于高性能CPT原子钟的理想算法。实际应用于CPT原子钟的实验结果与理论预期和实验仿真结果相一致。该方案有利于原子频标的工作状态调整和保持产品性能一致性。
The study of applying digital quadrature demodulation algorithm to phase locked loop of CPT atomic clock realized with a FPGA core is presented. Simulation results for this scheme with both MATLAB and QUARTUS2 reveal its good noise-resisting property and reliable demodulation ability. Therefore, it is an ideal scheme for high performance CPT atomic clock. Experimental result of application the scheme to CPT atomic clock consists with that from simulation. This scheme makes it easier to modify the operation state of atomic clock and keeps better consistency of products.
出处
《计量学报》
CSCD
北大核心
2010年第2期145-149,共5页
Acta Metrologica Sinica
基金
国家自然科学基金（10574141,10675162）
关键词
计量学
原子钟
锁相环路
数字正交解调
FPGA
Metrology
Atomic clock
Phase locked loop
Digital quadrature demodulation
FPGA
