摘要
A new NI （n^＋ charge islands） high voltage device structure based on E-SIMOX （epitaxy-the separation by implantation of oxygen） substrate is proposed. It is characterized by equidistant high concentration n＋-regions on the top interface of the dielectric buried layer. Inversion holes caused by the vertical electric field （Ev） are located in the spacing of two neighboring n^＋-regions on the interface by the force from lateral electric field （EL） and the compositive operation of Coulomb＇s forces with the ionized donors in the undepleted n^＋-regions. This effectively enhances the electric field of dielectric buried layer （EI） and increases breakdown voltage （VB）. An analytical model of the vertical interface electric field for the NI SOI is presented, and the analytical results are in good agreement with the 2D simulative results. EI = 568 V/μm and VB = 230 V of NI SOI are obtained by 2D simulation on a 0.375-μm-thick dielectric layer and 2-μm-thick top silicon layer. The device can be manufactured by using the standard CMOS process with addition of a mask for implanting arsenic to form NI. 2-μm silicon layer can be achieved by using epitaxy SIMOX technology （E-SIMOX）.
A new NI （n^＋ charge islands） high voltage device structure based on E-SIMOX （epitaxy-the separation by implantation of oxygen） substrate is proposed. It is characterized by equidistant high concentration n＋-regions on the top interface of the dielectric buried layer. Inversion holes caused by the vertical electric field （Ev） are located in the spacing of two neighboring n^＋-regions on the interface by the force from lateral electric field （EL） and the compositive operation of Coulomb＇s forces with the ionized donors in the undepleted n^＋-regions. This effectively enhances the electric field of dielectric buried layer （EI） and increases breakdown voltage （VB）. An analytical model of the vertical interface electric field for the NI SOI is presented, and the analytical results are in good agreement with the 2D simulative results. EI = 568 V/μm and VB = 230 V of NI SOI are obtained by 2D simulation on a 0.375-μm-thick dielectric layer and 2-μm-thick top silicon layer. The device can be manufactured by using the standard CMOS process with addition of a mask for implanting arsenic to form NI. 2-μm silicon layer can be achieved by using epitaxy SIMOX technology （E-SIMOX）.
基金
supported by the Major Project of the National Natural Science Foundation of China(No.60806025)
the Youth Teacher Foundation of University of Electronic Science and Technology of China(No.jx0721).
