摘要
介绍140万像素、每秒7.5帧高清高速数字摄像机的电路设计方案。该设计主要由SONY的CCD ICX205AK,Analog Devices模拟前端电路AD9923A以及Xilinx的FPGA XC3S1200E,TOKYO的JPEG压缩芯片TE3310RPF和ATMEL的ARM芯片AT91RM9200等组成。模拟前端电路AD9923A实现CCD水平和垂直时序的产生,CCD的放大,CCD信号的模数转换三大功能;CCD ICX205AK输出信号经模拟前端电路AD9923A进行放大和模数变换后,输入到FPGA进行数据格式处理,生成YUV信号输入到压缩芯片进行JPEG压缩,然后由ARM通过网络将压缩数据传送到客户端。实验结果表明,该设计方案每秒可以采集、压缩、传输140万像素图像7.5帧。
A circuit of high-resolution digital video camera, supporting 1.4 mega pixels and 7.5 frames per second was presented. ICX205AK is used as CCD sensor, AD9923A is used as the analog front end, and other chips include XC3S1200E and TE3310RPF. The AD9923A converts CCD analog signal to digital signal, and the digital signals are sent to XC3S1200E which converts Bayer signals to YUV signals. The YUV signals are input to TE3310RPF to generate JPEG data. AT91RM9200 sends the JPEG data to network. The testing results show that image can be collected, compressed, and transmitted with 1.4 mega pixels image 7.5 frames per second by this design.
出处
《激光与光电子学进展》
CSCD
北大核心
2010年第3期120-124,共5页
Laser & Optoelectronics Progress
基金
国家自然科学基金重点项目(60736046)
国家863计划(2006AA12A104)资助课题
