摘要
针对雷达系统后端数据处理的软硬件和计算时间的要求,研制了论文所述的数据处理单元。文章首先介绍了基于软件无线电结构的数据处理单元结构,分析了基于带通采样的中频数字化方法,基于分布式算法的FIR滤波器和二维分解算法的超长FFT的FPGA实现模块,并完成了仿真。该处理单元具有高速实时大数据量处理能力,设计结构体现了很好的开放性、灵活性和兼容性的特点。
According to the hardware, the software and the real time requirement of the passive radar receive system, it discussed the processor architecture based on Software Define Radio and analyzed emphasis on the each signal processing module, including IF digitization based on passband sampling technology, FIR filter pre-processing and ultra-long FFT based on two-dimension Decomposition algorithm in FPGA. Through the simulation and experiments, the signal processing module fully shows flexibility, open- ness and compatibility.
出处
《核电子学与探测技术》
CAS
CSCD
北大核心
2010年第1期88-92,共5页
Nuclear Electronics & Detection Technology
