摘要
提出了一种线性相位FIR滤波器分布式算法FPGA实现的改进结构。基于4输入查找表(4-input LUT)的分布式算法(DA)在FIR滤波器中的使用已经有效地提高了滤波器的运行速度与资源利用率。针对线性相位FIR滤波器的系数特点,通过对滤波器输入移位寄存器的改进设计,减少了DA算法的存储器使用,进一步节省了资源。改进的滤波器已经在Xilinx Spartan3系列的FPGA芯片上成功实现,分析结果显示此类滤波器与传统的滤波器分布式算法实现相比有更高的资源利用率和更快的运行时钟速率。
This paper presents a new linear-phase FIR filter designing method using distribute arithmetic （DA）. DA based 4- input LUT used to implement the FIR filter has increased the maximum frequency and enhanced the area-efficiency. The proposed design changes the shift-register architecture with the coefficient characteristic of linear-phase FIR filters, and reduces the memory for DA. The new design is implemented on a Xilinx Spartan3 XCA000 FPGA using verilog HDL. The results confirm that the proposed design can implement a linear-phase FIR filter with smaller area usage than the original one.
出处
《舰船电子工程》
2010年第2期57-60,106,共5页
Ship Electronic Engineering
