摘要
随着集成电路工艺和规模的飞速发展,使得VLSI测试变得日益困难,因此测试技术成为VLSI领域的一个重要研究课题。在分析VLSI测试的瓶颈问题基础上,介绍了几种电路分块算法,分析了分块算法对于VLSI测试的必要性。利用分块算法将原始电路划分为若干子块有利于采用不同BIST结构对子块进行测试,使得一定时间内电路翻转次数降低,而功耗也随之降低;通过比较并行BIST和扫描BIST的实验结果,发现并行BIST获得的系统故障覆盖率高于扫描BIST。
With rapid development of integrated circuit technology and scale, VLSI testing became more and more difficult. So the test technology became one of the important problem in VLSI aera. This paper introduced several kinds of circuit partitioning algorithm on the basis of analying the bottleneck problem of VLSI test, and analysed the necessity Of circuit partitioning algorithm for VLSI test. The strategy consists in partitioning the original circuit into subcircuits so that each subcircuit can be successicely tested through different BIST scheme. The switching activity in a time interval as well as power are reduced. The results show that the fault coverage obtained with the parallel BIST scheme is higher than the scan-based BIST by comparing two BIST architectures.
出处
《国外电子测量技术》
2010年第1期27-29,45,共4页
Foreign Electronic Measurement Technology
关键词
分块
超图分解
并行遗传算法
内建自测试
partitioning
hypergraph partitioning
parallel genetic algorithms
BIST
