摘要
锁相环器件的数字集成化,使得全数字锁相环在数字通信中得到了极为广泛的应用;传统的K模计数器构成的数字锁相环虽然实现简单,但无法同时顾及到环路锁定时间和相位抖动噪声,因此设计了一种基于FPGA的智能控制K模计数器模值的数字锁相环;该设计能够在环路工作的不同阶段自动调整K模计数器的模值大小,从而实现了在缩短环路锁定时间的同时减小相位噪声误差;实际应用结果表明,该设计在低频段的频率跟踪应用中,系统的捕获时间有明显的缩短,相位抖动噪声也得到良好的控制。
With the integrated digital PI,L development, All Digital Phase-locked Loop is wildly used in digital communication. Although the traditional DPLL composed of K modulus counter can be implemented easily and conveniently, it has to take long time to lock the input frequency if we need to lower the impact of phase dithering on loop. Now this article introduces a DPLL with intelligent modulus controller based on FPGA. The DPLL is designed to adjust the value of K-modulus counter automatically when the loop works at different stages. Hence, we can reduce the error of phase dithering while we want to make the loop work at locked stage as soon as possible. The application shows that the lock time of DPLL is shortened and the phase dithering is decreased when it is used in low frequency system.
出处
《计算机测量与控制》
CSCD
北大核心
2010年第1期75-77,共3页
Computer Measurement &Control
关键词
FPGA
数字锁相环
K模计数器
智能模值控制
FPGA
DPLL （Digital Phase-locked Loop）
K modulus counter
Intelligent modulus controller
