摘要
为了提高姿态确定算法的计算速度,在分析了现有确定性姿态确定算法的基础上,设计出了基于FPGA(Field Programmable GateArray)的姿态确定算法IP(Intellectual Property)核。在该程序的各主要模块中,使用状态机控制存储器向不同运算器读取或写入数据,从而完成姿态确定的计算。程序采用流水线技术,在Quartus II中对其进行建模与综合,最后通过硬件仿真工具ModelSim进行仿真。同时在NIOS II上用软件实现了姿态确定算法。仿真结果表明,硬件在第一次姿态确定完成后的运算周期约为20μs,远远快于软件500μs的运行时间。
In order to improve the calculating speed of attitude determination algorithm,the IP （Intellectual Property） core of attitude determination algorithm based on FPGA （Field Programmable Gate Array） was designed on the analysis of deterministic attitude determination algorithm in existence.In each module of the program,the state machine was adopted to complete the computation of attitude determination by controlling RAM （Random Access Memory） to read or write data to different arithmetic units.With pipeline techniques,the program was modeled and synthesized in Quartus II,and finally it was simulated in the hardware simulation tool ModelSim.The attitude determination algorithm was implemented in NIOS II with software in the meantime.The result of simulation shows that,the calculation period of the hardware is about 20μs after finishing the first attitude determination,which is much quicker than the software＇s runtime,500μs.
出处
《系统仿真学报》
CAS
CSCD
北大核心
2009年第24期7948-7951,共4页
Journal of System Simulation
基金
教育部博士点基金(20070699004)
