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频率合成器中Σ-Δ调制器的设计与实现 被引量：2

Design and Implementation of a Sigma-Delta Modulator in the Frequency Synthesizer
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摘要 本文首先介绍了Σ-Δ调制技术的基本原理,分析了一阶及高阶Σ-Δ调制器,最后结合一阶Σ-Δ调制器,给出了在FPGA器件上实现Σ-Δ调制器的设计。仿真结果表明,设计实现了Σ-Δ调制器,通过控制分频器实现了小数分频,方法简单易行。与运用Matlab软件仿真的结果完全一致,并进一步证实了高阶数字Σ-Δ调制对量化相位噪声的高通整形特性,从而有效地解决了小数分频频率合成器中的小数杂散问题,具有很高的实用性。 The principle of the sigma-delta modulation technology is introduced first in this paper. Then the first-order and the higher order sigma-delta modulators are analyzed, and finally a method for the sigma-delta modulator based on FP GA is proposed. This design of a sigma-delta modulator is correct and feasible. Simulation results show that the results from the sigma-delta modulator and the fractional-N divider by controling the frequency divider implemented by this method are well in accordance with the simulation results based on Matlab software. Then noise shaping characteristics of the higher-order sigma-delta modulator is further experimentally verified. The fractional spur introduced by the fractional-N frequency synthesizer can be suppressed by the loop filter of the phase-locked-loop,which is highly practicable.
作者 刘德建
机构地区 桂林电子科技大学信息与通信学院
出处 《计算机工程与科学》 CSCD 北大核心 2009年第12期121-123,共3页 Computer Engineering & Science
基金 国家自然科学基金资助项目(60472091) 教育部新世纪优秀人才支持计划资助项目(NCET-05-0754) 广西自然科学基金资助项目(桂科自0447093 0640168)
关键词 频率合成器 Σ-Δ调制器 现场可编程门阵列 frequency synthesizer sigma-delta modulator FPGA
分类号 TN74 [电子电信—电路与系统]
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参考文献4

  • 1Brian M, Conley R J. A Multiple Modulator Fractional Divider [J]. IEEE Trans on Instrumentation Measurement, 1991,40(3) :578-583.
  • 2Riley T A D, Copeland M A, Kwasniewski T A. Delta-Sigma Modulation in Fractional-N Frequency Synthesis [J ]. IEEE Journal of Solid-State Circuits, 1993,28(5): 553-559.
  • 3Shu K, Sanchez-Sinencio E,Maloberti F, et al. A Comparative Study of Digital XA Modulators for Fractional-n Synthesis[C]//Proc of ICECS'01, 2001 :1391-1394.
  • 4Chou W, Wong P W, Gray R M. Multistage Sigma-delta Modulation[J]. IEEE Trans on Information Theory, 1989, 35(4) :784-796.

同被引文献24

  • 1唐圣学,何怡刚,郭杰荣,李宏民,黄姣英,阳辉.基于Σ-Δ调制技术的信号发生器设计[J].湖南大学学报（自然科学版）,2007,34(5):44-48. 被引量：2
  • 2SI.EIMAN S B, ATAI.I.AHJ G, RODRIGUEZS, etul. Op- rimal ∑-△ modulator architectures for fractionaI-N frequency synthesis[J]. IEEE Transaclions on Very Large Scale Integra- tion Systems, 2010, 18(2):194-200.
  • 3FATAHI N, NABOVATI H. Design of low noise fractional-N frequency synthesizer using sigma-delta modulation technique [C]// Proceedings of 27th International Conference on Micro- electronics. New York: IEEE, 2010 369-372.
  • 4ZANUSO M, LEVANTINO S, SAMORI C, et al. A wide- band 3.6 GHz digital AE fractional-N PLL with phase interpo- lation divider and digital spur eancellation[J]. IEEE Journal of Solid-State Circuits, 2011, 46(3):627-638.
  • 5TEMPORITI E, WILTIN-WU C, BALDI D, etal. A 3 GHz fractional all-digital PLL with a 1. 8 MHz bandwidth imple- menting spur reduction techniques[J]. IEEE Journal of Solid- State Circuits, 2009, 44(3):824-834.
  • 6ZANUSO M, LEVANTINO S. Time-to-digital converter with 3-ps resolution and digital linearization algorithm [C]//Pro- ceedings of the ESSCIRC. New York: IEEE, 2010: 262- 265.
  • 7BORREMANS J, VENGATTARAMANE K, GIANNINI V, et al. A 86 MHz-to-12 GHz digltal-intensive phase-modulated fraetional-N PLL using a 15 pJ/shot 5 ps TDC in 40 nm digital CMOS[C]//Proceedings of 2010 IEEE ISSCC. New York: IEEE, 2010:480-481.
  • 8MADOGL10 P, ZANUSO M. Quantization effects in all-digit- al phase-locked loops[J]. IEEE Transactions on Circuits Sys- tem, 2007, 51(12):1120-1124.
  • 9WU Wang-hun, BAI Xue-fei. A 56.4-too63.4 GHz spurious- free all-digital Fraetional-N PLL in 65 nm CMOS[C]//Pro- eeedings of 2013 IEEE International Solid-State Circuits Con- ference. New York: IEEE, 2013: 352-354.
  • 10舒海勇.PLL频率综合器中整数和小数分频器设计与实现[D].南京:东南大学.2010.

引证文献2

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计算机工程与科学
2009年 第12期

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