期刊文献+

片上网络互联的划分测试 被引量:4

Division test of network-on-chip interconnects
在线阅读 下载PDF
导出
摘要 在伪穷举测试的基础上,提出了一种片上网络互联的划分测试。将片上的资源(主要是路由器和通道)按一定的方法划分为4个区,然后采用伪穷举测试的方法分别对每个分区进行测试。实验证明,随着芯片规模的增大,本方法比伪穷举测试减少了测试时间和测试包数,降低了测试功耗,缩小了片上报错的范围。另外,本文还在划分测试的基础上提出了一种错误定位的方法,可以将出错的路由器或通道定位到出错分区的具体位置。 A division test of network-on-chip interconnects based on the pseudo-exhaustive testing is present. The resources (mainly touters and channels) divided into four districts according to a certain method, and then the method of pseudo-exhaustive testing is used to test each partition respectively. The experiments show that this method can reduce the test time, the number of packages and the test power, and shrink the scope of error on chip comparing with the pseudo-exhaustive testing as the chip size increasing. At the same time, this method can also ease some prob- lems in a certain extent, such as the congestion and hot spots. In addition, the paper also present a method of locating error based on division testing, this method can locate the wrong routers or channels to the specific location of errorpartition.
出处 《电子测量与仪器学报》 CSCD 2009年第11期101-107,共7页 Journal of Electronic Measurement and Instrumentation
基金 国家自然科学基金(编号:60876028)资助项目 国家自然科学基金(编号:60633060)资助项目 安徽省自然科学基金(编号:090412034)资助项目
关键词 片上网络 单固定故障 伪穷举测试 划分测试 networks on chip stuck-at port fault pseudo-exhaustive test division test
  • 相关文献

参考文献8

  • 1高明伦,杜高明.NoC:下一代集成电路主流设计技术[J].微电子学,2006,36(4):461-466. 被引量:33
  • 2ZHANG L, HAN Y H, LI H W, et al. Fault Tolerance Mechanism in Chip Many-Core Processors[J].Tsinghua Science and Technology,2007,12(21).
  • 3NOLEN J M, RABI N M. Time-division-multiplexed test delivery for NoC systems[J].IEEE Design & Test of Computers,2008:44-51.
  • 4ALEXANDRE M A, BRIAO E.A scalable test strategy for network-on-chip routers[C].International Test Conference, Austin,2005:25.
  • 5TRAN X T, THONNAR Y. A design-for-test implementation of an asynchronous network-on-chip architecture and its associated test pattern generation and application [C]. International Symposium on Networks-on-Chip, Newcastle University,2008:149.
  • 6HOSSEINABADY M, BANAIYAN A. A concurrent testing method for NoC switches[C].Design Automation & Test in Europe, Munich,2006:244.
  • 7SEDGHI M, KOOPAHI E, ALAGHI A. An NoC test strategy based on flooding with power, test time and coverage considerations[C]. International Conference on VLSI Design, Hyderabad, 2008:409.
  • 8CRISTIAN G, PANDE P, WANG B SH. Methodologies and algorithms for testing switch-based NoC interconnects [C]. International Symposium on Defect and Fault Tolerance in VLSI Systems, Washington,2005:238-246.

二级参考文献12

  • 1ITRS.International Technology Roadmap for Semiconductors[EB/OL].http://public.itrs.net.2003.
  • 2ITRS.International Technology Roadmap for Semiconductors[EB/OL].http://public.itrs.net.1999.
  • 3Tully J,Gordon R,Bruederle S,et al.Hype cycle for semiconductors,2004[R].Gartner research's Technical Report,2004.ID Number:G00120909:2-3.
  • 4Benini L,De Micheli G.Networks on chips:a new SoC paradigm[J].Computer,2002,35(1):70-78.
  • 5Jerraya A,Wolf W,eds.Multiprocessor systems-on-chips[M].San Francisco,Morgan Kaufman / Elsevier,2004.
  • 6Hemani A,Jantsch A,Kumar S,et al.Network on chip:an architecture for billion transistor era[A].Proc IEEE NorChip Conf[C].Turku,Finland.2000.166-173.
  • 7Guerrier P,Grenier A.A generic architecture for on-chip packet-switched interconnections[A].Des Autom and Test in Euro Conf[C].Paris,France.2000.250-256.
  • 8Pham D.The design and implementation of a first-gen-eration CELL processor[A].Int Sol Sta Circ Conf[C].San Francisco,CA,USA.2005.184-185.
  • 9Glossner G.The sandbridge sandblaster SB3000 multithreaded CMP platform[A].5th Int Forum Appl Spec Multi-Processor SoC[C].Relais de Margaux,France.2005.18-23.
  • 10Jantsch A,Tenhunen H.Networks on chip[M].Dordrecht:Kluwer Academic Publishers,2003.

共引文献32

同被引文献53

  • 1杨俊安,庄镇泉.量子遗传算法研究现状[J].计算机科学,2003,30(11):13-15. 被引量:53
  • 2高明伦,杜高明.NoC:下一代集成电路主流设计技术[J].微电子学,2006,36(4):461-466. 被引量:33
  • 3International Technology Roadmap.International Technology Roadmap for Semiconductors[R].2009.
  • 4CHANDRA A,CHAKRABARTY K.Low-power scan testing and test data compression for system on a chip[J].IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems,2002,21(5):597-604.
  • 5XIE Y,LOH G,BLACK B,et al.Design space exploration for 3D architectures[J].ACM Journal on Emerging Technologies in Computing Systems (JETC),2006,2(2):65-103.
  • 6DONG X Y,XIE Y.System-level cost analysis and design exploration for three-dimensional[C].2009 Asia and South Pacific Design Automation Conference,2009:235-241.
  • 7RAHMAN A,REIF R.System-level performance evaluation of three-dimensional integrated circuits[J].IEEE Transaction VLSI Systems,2000,8(6):671-678.
  • 8MARINISSEN E J,OEL S K,LOUSBERG M.Wrapper design for embedded cores test[C].Atlantic City:IEEE International Test Conference,2000:911-920.
  • 9LI J,LIN H,XU Q.Test architecture design and optimization for three-dimensional SoCs[C].Conference on Design,Automation and Test in Europe,2009.
  • 10WU X X,FALKENSTERN P,XIE Y.Scan chain design for three-dimensional integrated circuits[C].25th International Conference on Computer Design,2007:208-214.

引证文献4

二级引证文献25

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部