摘要
去块效应滤波在有效改善图像质量和压缩效率的同时,也引入了极大的计算复杂度,另外去块滤波过程需要从片外存储器读取待滤波的数据并将滤波后的数据写入片外存储器,这对于读写时钟有很高的要求,为了改善去块滤波提出了一种基于FPGA的改进的滤波算法。相对于基本的滤波方法,可以尽快得到滤波结果,减小片内缓存的中间数据量,同时减少整个滤波过程所需要的时钟周期数,采用5级流水线电路结构,具有较高的数据吞吐量,整个设计划分为多个功能模块,全部采用Verilog HDL硬件描述语言实现,通过matlab和modelsim联合仿真验证。可以满足对H264图像实时解码的要求。
The deblocking filter in the H. 264 video coding standard can improve video quality but with huge computational complexity. A high performance, small area deblocking filter was designed based on a deblocking algorithm, which executes read/write operations on external memory with filtering computations in parallel based on an advanced filtering order. Our design has less area, clock and better performance than other deblocking filters, the circuit use 5 pipline and has a higher data throughput, the whole design divided into several functional modules, which are fulfilled with VERILOG. Matlab joint modelsim simulation. Image of H264 to meet the requirements of realtime decoding
出处
《电子测量技术》
2009年第10期117-120,共4页
Electronic Measurement Technology
关键词
去块滤波
滤波强度
虚假边界
流水线
deblock filter
filter strength
false boundary
pipline
