摘要
功耗分析是低功耗逻辑综合的一个重要步骤。ＣＭＯＳ组合逻辑电路的功耗分析由于电路节点之间存在相关性而变得复杂。采用两两相关的方法对电路内部节点的相关性进行建模，并且对相关性进行划分强弱分别进行处理，从而提高了计算的精度。同时为了降低计算的空间复杂度，对电路采用了按逻辑深度分级计算的方法，使计算的复杂度并不与电路规模直接相关。对ＩＳＣＡＳ’８５基本测试电路（ｂｅｎｃｈｍａｒｋ）的实验结果说明此方法可以有效地用于较大规模的组合逻辑电路的功耗分析。
Power estimation is an important step in low power logic synthesis. Power estimation for CMOS combinational circuits is complicated by the correlation among internal signals. This paper takes the pair wise correlation model and deals with strong and weak correlation types differently to improve the accuracy of the computation. On the other hand, to lower the space complexity, power analysis was executed according to the depth of the gate in the circuit, starting from the primary inputs, ending at the primary outputs, thus making the complexity of the calculation not directly related to the scale of the circuit. The method was tested using ISCAS'85 benchmark circuits, and the results show that the approach can be used in power analysis of large scale circuits.
出处
《清华大学学报（自然科学版）》
EI
CAS
CSCD
北大核心
1998年第9期32-35,共4页
Journal of Tsinghua University(Science and Technology)
基金
国家"九五"重点科技攻关项目
