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一种回声消除和噪声抑制SoC芯片

An Echo Cancellation and Noise Suppression SoC Chip
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摘要 提出了一种回声消除和噪声抑制算法,采用改进的自适应步长非线性滤波技术,用单芯片对该算法进行了实现.用180nm 3.3V/1.8V 6层金属混合信号CMOS工艺流片,可达70dB的声学回声消除性能,噪音消除达20dB,侧音消除达30dB.该芯片包含1个16位DSP、3个14位Σ-ΔADC、2个16位Σ-ΔDAC、以及内置ROM和RAM等,并集成有USB、UART、I^2C和PCM等接口.测试结果表明该芯片具有全双工和远距离免提的功能,支持双路麦克风输入,技术规范符合G.165国际标准.该芯片功耗低,外围电路简单,自适应能力强,可广泛应用于蓝牙车载免提通信、GPS和即时通讯等领域. An echo cancellation and noise suppression algorithm is presented by using improved adaptive step-size non-linear filter technology,and a single-chip implementation for this algorithm is proposed. This chip is fabricated in a 3.3V/1.8V 6-metal 180 nm mixed-signal CMOS process,and its acoustic echo cancellation performance can reach 70 dB,noise suppression performance is 20 dB and side tone cancellation is 30 dB. This chip includes a 16-bit DSP, three 14-bit sigma-delta ADC, two 16-bit sigma-delta DAC and embedded ROMs and RAMs, which also provides USB, UART, I^2C and PCM interfaces. Experimental results show that the chip supports full-duplex mode,faraway hand-flee function and dual microphones input and it complies with ITU-T G. 165 standard. With very low power consumption, simple peripheral circuits and strong self adaptation capability, it can be widely used in various applications such as portable Bluetooth hand-free car kit, GPS and instant communication.
出处 《电子学报》 EI CAS CSCD 北大核心 2009年第8期1789-1793,共5页 Acta Electronica Sinica
基金 国家科技部技术创新基金(No.07C26213101259)
关键词 回声消除 噪声抑制 免提通信 SOC芯片 echo cancellation noise suppression hand- free communication system on chip(SoC)
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参考文献16

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