摘要
针对系统对于SDH性能告警处理方面的需求,利用Altera低成本的FPGA开发设计了基于NiosⅡ嵌入式CPU的处理平台,利用SOPC Builder创建了NiosⅡ SoC硬件系统,开发了嵌入式软件,从而实现对外围ASIC芯片的配置和性能告警处理算法。
by using low configuration software. To meet the cost Ahera of external requirement of SDH performance alarm processing, a platform based on NiosII was designed FPGA. ASICs The hardware system of NiosII SoC was created by using SOPC Builder. The and the processing of performance alarm were implemented in NiosII Embedded
出处
《中国集成电路》
2009年第7期25-27,共3页
China lntegrated Circuit
