摘要
介绍了数字通信中码元同步模块设计中的一种基于内插码元同步的设计方案。在分析码元同步原理的基础上提出了一种内插和Gardner定时误差检测相结合实现码元同步电路的设计方案,通过仿真分析验证了该设计方案的正确性和可行性。结果表明该方案具有抗干扰性、稳定性好,同步建立时间短,同步保持时间长,同步带宽宽的优点。
A symbol synchronization program design based on interpolation is introduced. A circuit structure for symbol synchronizing is proposed, on the basis of cubic Interpolation and Gardner timing error detection. Through the simulation analysis of this design method, the correctness and feasibility has been verified. The result shows that this method has a good anti-jamming and good stability. The estab- lishment time of synchronization is very short, while it can maintain a long synchronization with a wide bandwidth.
出处
《北京信息科技大学学报（自然科学版）》
2009年第2期87-90,共4页
Journal of Beijing Information Science and Technology University
基金
北京市教育委员会科技发展计划资助项目(KM200710772001)
关键词
码元同步
内插
GARDNER算法
采样
symbol synchronizer
interpolation
Gardner algorithm
sampling
