摘要
用硬件实现数据加密已成为信息安全的主流方向。本文提出了一种基于FPGA的低成本的AESIP核的实现方案。该方案轮内部系统资源共用,减少了系统资源的占用。输入密钥与输入数据复用8位数据总线,减少了硬件的接口数量。采用VHDL语言编程,利用QUARTUS II 7.0进行了综合和布线,并进行了板级验证。器件采用CYCLONE II EP2C35F672,占用25个引脚,实验测试表明在50MHz时钟频率下可以进行加密解密操作。
Hardware implementation of data encryption has become the mainstream in information security field. An architecture for low cost AES IP core based on FPGA is proposed in this paper. The architecture is being developed and prototyped in QUARTUS II 7.0 using VHDL and cyclone II EP2C35F672 FPGA from Ahera. The architecture is implemented using 25 I/Os. The encryption or decryption is performed with 50MHz clock frequency.
出处
《微计算机信息》
2009年第17期240-242,共3页
Control & Automation
基金
鞍山市科委资助项目(2006SH16)
