期刊文献+

适用于宽带电力线通信的LDPC码译码算法的研究 被引量:4

Research on decoding algorithn for LDPC codes in power line channels
在线阅读 下载PDF
导出
摘要 用A类噪声模型模拟电力线信道中的脉冲噪声环境,采用LDPC码来抑制A类噪声信道(AWAN)中的窄带脉冲噪声。针对A类噪声信道的特性,将信道初始信息的对数似然比(LLR)公式进行适当修改,完成对原有Log-BP译码算法的改造。通过蒙特卡罗仿真与原有的Log-BP译码算法的译码性能进行比较分析,结果表明,在对A类噪声模型的参数Γ和A取值合理的情况下,在AWAN信道上改造后的Log-BP译码算法的误码率性能提高近11dB。 LDPC (low density parity check)codes to AWAN (additive white class a noise)channels is adopted, which is usually used as the model of impulsive noise environment of power line channels. A modification for the LLR ( likelihood ratio ) of the initial information to Log-BP ( log domain belief propagation ) decoding, which is suitable for AWAN channels, is proposed. Finally, compared with the original Log-BP decoding, it shows the BER (bit error rate) performance of the modified Log-BP decoding over AWAN channels by Monte-Carlo simulation,the result shows that the modified Log-BP decoding has about 11 dB gain with the reasonable values A and Γ.
出处 《电子测量与仪器学报》 CSCD 2009年第3期27-32,共6页 Journal of Electronic Measurement and Instrumentation
基金 华北电力大学博士基金(编号:200812004)资助项目
关键词 电力线上网 AWAN LDPC Log-BP power line communication AWAN LDPC Log-BP
  • 相关文献

参考文献9

  • 1缪德山,李道本.一种改进的LDPC码译码算法[J].电子测量与仪器学报,2007,21(6):19-21. 被引量:4
  • 2MIDDLETON D. Statistical-physical model of electromag- netic interference [ J]. IEEE Trans. Electromagn. Compa. ,1977,EMC-19(3) :106-126.
  • 3KIM S, SOBELMAN G E, MOON J. Parallel VLSI architectures for a class of LDPC codes [ C ]. Circuits and Systems, IEEE International Symposium on,2002,2:93-96.
  • 4GALLAGER R G. Low density parity-check codes [ M ]. MIT Press, Cambridge, MA, 1963.
  • 5BERROU C, GLAVIEUS A. Near optimum error correcting coding and decoding: turbo-codes [ J ]. IEEE Trans. Commun, 1996,44 : 1261-1271.
  • 6YAMAUCHI K, TAKAHASHI N, Maeda M. Parameter measurement of class A interference on power line [J].Trans. IEICE, 1989 ,E 72( 1 ) :7-9.
  • 7TANNER M. A recursive approach to low complexity codes [ J ]. IEEE Trans. Inform. Theory, 1981, IT-27 : 533-547.
  • 8PROAKIS J G. Digital communications [ M ]. McGraw- Hill, 2001.
  • 9WADAYAMA T A. Coded modulation scheme based on low density check codes [ J ]. IEICE Trans. Fundamentals, 2001, E84 -A.

二级参考文献6

  • 1Gallager R G. Low density parity check codes[J]. IEEE Transaction on Information Theory, 1962, 8 ( 1 ) :21 - 28.
  • 2Mackay D J C. Good error-correcting codes based on very Sparse matrices [ J ]. IEEE Transaction on Inform Theory, 1999,45 (2) :399 - 431.
  • 3Mackay D J C, Postol M S. Weakness of Margulis and Ramanujan-Margulis low density parity-check codes [ J ]. Electronic Notes in Theoretical Computer Science, 2003, 74:1 -8.
  • 4Varnica N. Iteratively decodable codes for memoryless and intersymbol interference channels [ D ]. Ph. d Thesis. Cambridge, Massachusetts, 2005 , 109 - 142.
  • 5M-R Sadeghi, A H. Banihashemi, and D Panario. Lowdensity parity check and lattice: Constructions and Decoding analysis [ J ]. IEEE Trans Inform Theory,2006,52(10) :4481-4496.
  • 6林家儒,吴伟陵,冯志勇.Turbo码译码算法在频率选择性信道中的修正[J].北京邮电大学学报,2001,24(1):6-11. 被引量:6

共引文献3

同被引文献47

  • 1GY/T220.7-2008,移动多媒体广播第7部分:接收解码终端技术要求[S].北京:国家广电总局广播电视规划院.2008.
  • 2GALLAGER R.Low-density parity-check codes[J].IEEE Trans.on Inform.Theory,1962,8(3):21-28.
  • 3CHUNG S Y,FORNEY G D,URBANKE R.On the design of low-density parity check codes within 0.0045 dB of the Shannon limit[J].IEEE Comm.Letters,2001,5(2):58-60.
  • 4MACKAY D J C,NEAL R M.Near Shannon limit performance of low-density parity check codes[J].IEEE Electron.Letters,1996,32(18):1645.
  • 5MACKAY D J C.Good error-correcting codes based on very sparse matrices[J].IEEE Trans.on Inform.Theory,1999,45(2):399-432.
  • 6XIAO Y H,ELEFTHERIOU E.Efficient implementa-tions of the sum-product algorithm for decoding LDPC codes[C].IEEE Global Telecommunications Conference,25-29Nov,2001,1036.
  • 7MANSOUR M M.A turbo-decoding message-passing algorithm for sparse parity-check matrix codes[J].IEEE Transactions on Signal Processing,2006,54(11):4376-4392.
  • 8MANSOUR M M,SHANBHAG N R.High-throughput LDPC Decoders[J].IEEE Transactions on Very Large Scale Integration Systems,2003,11(12):976-997.
  • 9HOCEVAR D E.A reduced complexity decoder architecture via layered decoding of LDPC codes[C].IEEE Signal Processing Systems,13-15Otc,2004,107-112.
  • 10GUNNAM K K,CHOI G S,YEARY M B.A parallel VLSI architecture for layered decoding for array LDPC codes[C].20th International Conference on VLSI Design,6-10Jan,2007,738-743.

引证文献4

二级引证文献2

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部